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authorptitSeb <sebastien.chev@gmail.com>2025-06-25 10:49:03 +0200
committerptitSeb <sebastien.chev@gmail.com>2025-06-25 10:49:03 +0200
commitd67bc08d2dde39ae87befa2d4c031629a7c1ee62 (patch)
tree2c7c2190ca1fe8087c3880abd2fc0fe668294a09 /src
parente2b97768601209ba6769bd05dce7f8cfbd40d674 (diff)
downloadbox64-d67bc08d2dde39ae87befa2d4c031629a7c1ee62.tar.gz
box64-d67bc08d2dde39ae87befa2d4c031629a7c1ee62.zip
[ARM64_DYNAREC] Adjusted some UD flags in BLSMSK opcode
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_avx_0f38.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_avx_0f38.c b/src/dynarec/arm64/dynarec_arm64_avx_0f38.c
index 128863f4..cf5db08c 100644
--- a/src/dynarec/arm64/dynarec_arm64_avx_0f38.c
+++ b/src/dynarec/arm64/dynarec_arm64_avx_0f38.c
@@ -171,9 +171,14 @@ uintptr_t dynarec64_AVX_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, i
                     IFX(X_OF) {
                         IFNATIVE(NF_VF) {} else { BFCw(xFlags, F_OF, 1); }
                     }
-                    if (BOX64ENV(dynarec_test)) {
+                    if (BOX64ENV(dynarec_safeflags)) {
+                        // those are UD flags
                         IFX(X_AF) BFCw(xFlags, F_AF, 1);
-                        IFX(X_PF) BFCw(xFlags, F_PF, 1);
+                        if(BOX64ENV(cputype)) {
+                            IFX(X_PF) BFCw(xFlags, F_PF, 1);
+                        } else {
+                            IFX(X_PF) emit_pf(dyn, ninst, vd, x3);
+                        }
                     }
                     break;
 
@@ -211,9 +216,14 @@ uintptr_t dynarec64_AVX_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, i
                     IFX(X_OF) {
                         IFNATIVE(NF_VF) {} else { BFCw(xFlags, F_OF, 1); }
                     }
-                    if (BOX64ENV(dynarec_test)) {
+                    if (BOX64ENV(dynarec_safeflags)) {
+                        // those are UD flags
                         IFX(X_AF) BFCw(xFlags, F_AF, 1);
-                        IFX(X_PF) BFCw(xFlags, F_PF, 1);
+                        if(BOX64ENV(cputype)) {
+                            IFX(X_PF) BFCw(xFlags, F_PF, 1);
+                        } else {
+                            IFX(X_PF) ORRw_mask(xFlags, xFlags, 30, 0);   //mask=0x04
+                        }
                     }
                     break;