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| author | Yang Liu <numbksco@gmail.com> | 2024-04-14 15:26:42 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-14 09:26:42 +0200 |
| commit | d936c072eaeac7d42f5846fb5d46815a4b0f84bf (patch) | |
| tree | 12d7963c315c81dbd715bbec95d4b73d39dc5570 /src | |
| parent | 7dee075c107c4f61a3bcc27535636c8bb54d9098 (diff) | |
| download | box64-d936c072eaeac7d42f5846fb5d46815a4b0f84bf.tar.gz box64-d936c072eaeac7d42f5846fb5d46815a4b0f84bf.zip | |
[DYNAREC] Fixed shift xw macros (#1443)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/la64/la64_emitter.h | 30 | ||||
| -rw-r--r-- | src/dynarec/rv64/rv64_emitter.h | 31 |
2 files changed, 47 insertions, 14 deletions
diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h index 1bc4bf3d..a921643c 100644 --- a/src/dynarec/la64/la64_emitter.h +++ b/src/dynarec/la64/la64_emitter.h @@ -292,6 +292,16 @@ f24-f31 fs0-fs7 Static registers Callee } \ } while (0) +#define SLLxw(rd, rj, rk) \ + do { \ + if (rex.w) { \ + SLL_D(rd, rj, rk); \ + } else { \ + SLL_W(rd, rj, rk); \ + ZEROUP(rd); \ + } \ + } while (0) + // Shift Left Immediate #define SLLIxw(rd, rs1, imm) \ do { \ @@ -299,16 +309,18 @@ f24-f31 fs0-fs7 Static registers Callee SLLI_D(rd, rs1, imm); \ } else { \ SLLI_W(rd, rs1, imm); \ + ZEROUP(rd); \ } \ } while (0) // Shift Right Logical Immediate -#define SRLIxw(rd, rs1, imm) \ - do { \ - if (rex.w) { \ - SRLI_D(rd, rs1, imm); \ - } else { \ - SRLI_W(rd, rs1, imm); \ - } \ +#define SRLIxw(rd, rs1, imm) \ + do { \ + if (rex.w) { \ + SRLI_D(rd, rs1, imm); \ + } else { \ + SRLI_W(rd, rs1, imm); \ + if (imm == 0) ZEROUP(rd); \ + } \ } while (0) // Shift Right Arithmetic Immediate @@ -318,6 +330,7 @@ f24-f31 fs0-fs7 Static registers Callee SRAI_D(rd, rs1, imm); \ } else { \ SRAI_W(rd, rs1, imm); \ + ZEROUP(rd); \ } \ } while (0) @@ -327,6 +340,7 @@ f24-f31 fs0-fs7 Static registers Callee ROTRI_D(rd, rs1, imm); \ } else { \ ROTRI_W(rd, rs1, imm); \ + ZEROUP(rd); \ } \ } while (0) @@ -1857,6 +1871,8 @@ LSX instruction starts with V, LASX instruction starts with XV. ST_D(rd, rj, imm12); \ } while (0) +#define NEG_D(rd, rs1) SUB_D(rd, xZR, rs1) + #define SUBxw(rd, rj, rk) \ do { \ if (rex.w) \ diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h index 87e5be54..a32f763e 100644 --- a/src/dynarec/rv64/rv64_emitter.h +++ b/src/dynarec/rv64/rv64_emitter.h @@ -450,8 +450,22 @@ f28–31 ft8–11 FP temporaries Caller // rd = rs1>>rs2 arithmetic #define SRAW(rd, rs1, rs2) EMIT(R_type(0b0100000, rs2, rs1, 0b101, rd, 0b0111011)) -#define SLLxw(rd, rs1, rs2) EMIT(R_type(0b0000000, rs2, rs1, 0b001, rd, rex.w ? 0b0110011 : 0b0111011)) -#define SRLxw(rd, rs1, rs2) EMIT(R_type(0b0000000, rs2, rs1, 0b101, rd, rex.w ? 0b0110011 : 0b0111011)) +#define SLLxw(rd, rs1, rs2) \ + if (rex.w) { \ + SLL(rd, rs1, rs2); \ + } else { \ + SLLW(rd, rs1, rs2); \ + ZEROUP(rd); \ + } + +#define SRLxw(rd, rs1, rs2) \ + if (rex.w) { \ + SRL(rd, rs1, rs2); \ + } else { \ + SRLW(rd, rs1, rs2); \ + ZEROUP(rd); \ + } + #define SRAxw(rd, rs1, rs2) \ if (rex.w) { \ SRA(rd, rs1, rs2); \ @@ -468,15 +482,17 @@ f28–31 ft8–11 FP temporaries Caller SLLI(rd, rs1, imm); \ } else { \ SLLIW(rd, rs1, imm); \ + ZEROUP(rd); \ } // Shift Right Logical Immediate, 32-bit, sign-extended #define SRLIW(rd, rs1, imm5) EMIT(I_type(imm5, rs1, 0b101, rd, 0b0011011)) // Shift Right Logical Immediate -#define SRLIxw(rd, rs1, imm) \ - if (rex.w) { \ - SRLI(rd, rs1, imm); \ - } else { \ - SRLIW(rd, rs1, imm); \ +#define SRLIxw(rd, rs1, imm) \ + if (rex.w) { \ + SRLI(rd, rs1, imm); \ + } else { \ + SRLIW(rd, rs1, imm); \ + if (imm == 0) ZEROUP(rd); \ } // Shift Right Arithmetic Immediate, 32-bit, sign-extended #define SRAIW(rd, rs1, imm5) EMIT(I_type((imm5) | (0b0100000 << 5), rs1, 0b101, rd, 0b0011011)) @@ -486,6 +502,7 @@ f28–31 ft8–11 FP temporaries Caller SRAI(rd, rs1, imm); \ } else { \ SRAIW(rd, rs1, imm); \ + ZEROUP(rd); \ } #define CSRRW(rd, rs1, csr) EMIT(I_type(csr, rs1, 0b001, rd, 0b1110011)) |