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| author | ptitSeb <sebastien.chev@gmail.com> | 2021-03-23 16:37:23 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2021-03-23 16:37:23 +0100 |
| commit | da47d3470589458dab298e7fa6d9f9b1fc886226 (patch) | |
| tree | a0edcb3513a1c800f7d67e63a2af2f1ad820f8d2 /src | |
| parent | ce5a5bf356d482e7d01b3b823962494b3d6e6fe2 (diff) | |
| download | box64-da47d3470589458dab298e7fa6d9f9b1fc886226.tar.gz box64-da47d3470589458dab298e7fa6d9f9b1fc886226.zip | |
[DYNAREC] Added 0F AE opcode
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/dynarec_arm64_0f.c | 55 | ||||
| -rwxr-xr-x | src/dynarec/dynarec_arm64_f30f.c | 9 |
2 files changed, 64 insertions, 0 deletions
diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c index 08eaedeb..27aec99a 100755 --- a/src/dynarec/dynarec_arm64_0f.c +++ b/src/dynarec/dynarec_arm64_0f.c @@ -376,6 +376,61 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin WBACK; break; + case 0xAE: + nextop = F8; + if((nextop&0xF8)==0xE8) { + INST_NAME("LFENCE"); + } else + if((nextop&0xF8)==0xF0) { + INST_NAME("MFENCE"); + } else + if((nextop&0xF8)==0xF8) { + INST_NAME("SFENCE"); + } else { + switch((nextop>>3)&7) { + case 0: + INST_NAME("FXSAVE Ed"); + fpu_purgecache(dyn, ninst, x1, x2, x3); + if((nextop&0xC0)==0xC0) { + DEFAULT; + } else { + addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0); + if(ed!=x1) {MOVx_REG(x1, ed);} + CALL(rex.w?((void*)fpu_fxsave64):((void*)fpu_fxsave32), -1); + } + break; + case 1: + INST_NAME("FXRSTOR Ed"); + fpu_purgecache(dyn, ninst, x1, x2, x3); + if((nextop&0xC0)==0xC0) { + DEFAULT; + } else { + addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0); + if(ed!=x1) {MOVx_REG(x1, ed);} + CALL(rex.w?((void*)fpu_fxrstor64):((void*)fpu_fxrstor32), -1); + } + break; + case 2: + INST_NAME("LDMXCSR Md"); + GETED(0); + STRw_U12(ed, xEmu, offsetof(x64emu_t, mxcsr)); + break; + case 3: + INST_NAME("STMXCSR Md"); + if((nextop&0xC0)==0xC0) { + ed = xRAX+(nextop&7)+(rex.b<<3); + LDRw_U12(ed, xEmu, offsetof(x64emu_t, mxcsr)); + } else { + addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0); + LDRw_U12(x4, xEmu, offsetof(x64emu_t, mxcsr)); + STRw_U12(x4, ed, fixedaddress); + } + break; + default: + DEFAULT; + } + } + break; case 0xAF: INST_NAME("IMUL Gd, Ed"); SETFLAGS(X_ALL, SF_PENDING); diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c index db2b8619..c7bd738a 100755 --- a/src/dynarec/dynarec_arm64_f30f.c +++ b/src/dynarec/dynarec_arm64_f30f.c @@ -138,6 +138,15 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n FMULS(d1, v0, d0); VMOVeS(v0, 0, d1, 0); break; + case 0x5A: + INST_NAME("CVTSS2SD Gx, Ex"); + nextop = F8; + GETGX(v0); + GETEX(v1, 0); + d0 = fpu_get_scratch(dyn); + FCVT_D_S(d0, v1); + VMOVeD(v0, 0, d0, 0); + break; case 0x5C: INST_NAME("SUBSS Gx, Ex"); |