[DYNAREC] Added 0F C6 opcode

1 files changed, 27 insertions, 0 deletions

diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c
index 27aec99a..f17ad3ac 100755
--- a/src/dynarec/dynarec_arm64_0f.c
+++ b/src/dynarec/dynarec_arm64_0f.c
@@ -630,6 +630,33 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             }

             break;

 

+        case 0xC6:

+            INST_NAME("SHUFPS Gx, Ex, Ib");

+            nextop = F8;

+            GETGX(v0);

+            if(!MODREG)

+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 1);

+            u8 = F8;

+            d0 = fpu_get_scratch(dyn);

+            // first two elements from Gx

+            for(int i=0; i<2; ++i) {

+                VMOVeS(d0, i, v0, (u8>>(i*2)&3));

+            }

+            // second two from Ex

+            if(MODREG) {

+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));

+                for(int i=2; i<4; ++i) {

+                    VMOVeS(d0, i, v1, (u8>>(i*2)&3));

+                }

+            } else {

+                for(int i=2; i<4; ++i) {

+                    ADDx_U12(x2, ed, (u8>>(i*2)&3)*4);

+                    VLD1_32(d0, i, x2);

+                }

+            }

+            VMOVQ(v0, d0);

+            break;

+

         default:

             DEFAULT;

     }