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| author | ptitSeb <sebastien.chev@gmail.com> | 2023-12-05 12:06:23 +0100 |
|---|---|---|
| committer | ptitSeb <sebastien.chev@gmail.com> | 2023-12-05 12:06:23 +0100 |
| commit | e26363dc0f923d87a81ad071725ec585777c1fe8 (patch) | |
| tree | 14d92f7b8ba0cf52934a4ec2e3636854a4a7d9ac /src | |
| parent | 5dbc8bf3834eafd1caa3f7127505e93b248dd046 (diff) | |
| download | box64-e26363dc0f923d87a81ad071725ec585777c1fe8.tar.gz box64-e26363dc0f923d87a81ad071725ec585777c1fe8.zip | |
[DYNAREC] Removed unused code in strongmem emulation
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_helper.h | 4 | ||||
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_private.h | 1 | ||||
| -rw-r--r-- | src/dynarec/dynarec_native_pass.c | 1 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_helper.h | 4 | ||||
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_private.h | 1 |
5 files changed, 4 insertions, 7 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h index 664ccaaf..2fbd8832 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.h +++ b/src/dynarec/arm64/dynarec_arm64_helper.h @@ -49,7 +49,7 @@ // Opcode has wrote (strongmem>1 only) #define SMWRITE2() if(box64_dynarec_strongmem>SMREAD_MIN) dyn->smwrite=1 // Opcode has wrote with option forced lock -#define SMWRITELOCK(lock) if(lock || (box64_dynarec_strongmem>SMWRITE_MIN /*&& (!ninst || dyn->smlastdmb!=ninst-1)*/)) {SMDMB();} else dyn->smwrite=1 +#define SMWRITELOCK(lock) if(lock || (box64_dynarec_strongmem>SMWRITE_MIN)) {SMDMB();} else dyn->smwrite=1 // Opcode might have wrote (depend on nextop) #define SMMIGHTWRITE() if(!MODREG) {SMWRITE();} // Start of sequence @@ -57,7 +57,7 @@ // End of sequence #define SMEND() if(dyn->smwrite && box64_dynarec_strongmem) {if(box64_dynarec_strongmem){DSB_ISH();}else{DMB_ISH();}} dyn->smwrite=0; dyn->smread=0; // Force a Data memory barrier (for LOCK: prefix) -#define SMDMB() if(box64_dynarec_strongmem){DSB_ISH();}else{DMB_ISH();} dyn->smwrite=0; dyn->smread=1; dyn->smlastdmb = ninst +#define SMDMB() if(box64_dynarec_strongmem){DSB_ISH();}else{DMB_ISH();} dyn->smwrite=0; dyn->smread=1 //LOCK_* define #define LOCK_LOCK (int*)1 diff --git a/src/dynarec/arm64/dynarec_arm64_private.h b/src/dynarec/arm64/dynarec_arm64_private.h index e73a01f4..acbbe2e8 100644 --- a/src/dynarec/arm64/dynarec_arm64_private.h +++ b/src/dynarec/arm64/dynarec_arm64_private.h @@ -108,7 +108,6 @@ typedef struct dynarec_arm_s { size_t insts_size; // size of the instruction size array (calculated) uint8_t smread; // for strongmem model emulation uint8_t smwrite; // for strongmem model emulation - uint32_t smlastdmb; // for strongmem model 3+ uintptr_t forward; // address of the last end of code while testing forward uintptr_t forward_to; // address of the next jump to (to check if everything is ok) int32_t forward_size; // size at the forward point diff --git a/src/dynarec/dynarec_native_pass.c b/src/dynarec/dynarec_native_pass.c index b8039f5b..29d11d0e 100644 --- a/src/dynarec/dynarec_native_pass.c +++ b/src/dynarec/dynarec_native_pass.c @@ -43,7 +43,6 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int dyn->forward_to = 0; dyn->forward_size = 0; dyn->forward_ninst = 0; - dyn->smlastdmb = ~0; fpu_reset(dyn); ARCH_INIT(); int reset_n = -1; diff --git a/src/dynarec/rv64/dynarec_rv64_helper.h b/src/dynarec/rv64/dynarec_rv64_helper.h index 0a8de602..f6c5ea20 100644 --- a/src/dynarec/rv64/dynarec_rv64_helper.h +++ b/src/dynarec/rv64/dynarec_rv64_helper.h @@ -50,7 +50,7 @@ // Opcode has wrote (strongmem>1 only) #define SMWRITE2() if(box64_dynarec_strongmem>SMREAD_MIN) dyn->smwrite=1 // Opcode has wrote with option forced lock -#define SMWRITELOCK(lock) if(lock || (box64_dynarec_strongmem>SMWRITE_MIN /*&& (!ninst || dyn->smlastdmb!=ninst-1)*/)) {SMDMB();} else dyn->smwrite=1 +#define SMWRITELOCK(lock) if(lock || (box64_dynarec_strongmem>SMWRITE_MIN)) {SMDMB();} else dyn->smwrite=1 // Opcode might have wrote (depend on nextop) #define SMMIGHTWRITE() if(!MODREG) {SMWRITE();} // Start of sequence @@ -58,7 +58,7 @@ // End of sequence #define SMEND() if(dyn->smwrite && box64_dynarec_strongmem) {FENCE();} dyn->smwrite=0; dyn->smread=0; // Force a Data memory barrier (for LOCK: prefix) -#define SMDMB() FENCE(); dyn->smwrite=0; dyn->smread=1; dyn->smlastdmb = ninst +#define SMDMB() FENCE(); dyn->smwrite=0; dyn->smread=1 // LOCK_* define #define LOCK_LOCK (int*)1 diff --git a/src/dynarec/rv64/dynarec_rv64_private.h b/src/dynarec/rv64/dynarec_rv64_private.h index c3274ded..b7058c9a 100644 --- a/src/dynarec/rv64/dynarec_rv64_private.h +++ b/src/dynarec/rv64/dynarec_rv64_private.h @@ -118,7 +118,6 @@ typedef struct dynarec_rv64_s { size_t insts_size; // size of the instruction size array (calculated) uint8_t smread; // for strongmem model emulation uint8_t smwrite; // for strongmem model emulation - uint32_t smlastdmb; // for strongmem model 3+ uintptr_t forward; // address of the last end of code while testing forward uintptr_t forward_to; // address of the next jump to (to check if everything is ok) int32_t forward_size; // size at the forward point |