about summary refs log tree commit diff stats
path: root/src
diff options
context:
space:
mode:
authorptitSeb <sebastien.chev@gmail.com>2025-01-01 16:39:30 +0100
committerptitSeb <sebastien.chev@gmail.com>2025-01-01 16:39:30 +0100
commitebf03f88786fe43b23dd2cb9d5ba753d660b3ce2 (patch)
tree795182861aa20f6b311e6ad354056a7d9c349abe /src
parentd7dbee5126ebc72bcaa301c51cfacb6bd4a7e35c (diff)
downloadbox64-ebf03f88786fe43b23dd2cb9d5ba753d660b3ce2.tar.gz
box64-ebf03f88786fe43b23dd2cb9d5ba753d660b3ce2.zip
[ARM64_DYNAREC] Improved ADCX opcode
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_660f.c24
1 files changed, 19 insertions, 5 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index 66b17e6e..0f2dd1fe 100644
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -924,13 +924,27 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                     SETFLAGS(X_CF, SF_SUBSET);

                     GETED(0);

                     GETGD;

-                    MRS_nzcv(x3);

-                    BFIx(x3, xFlags, 29, 1); // set C

-                    MSR_nzcv(x3);      // load CC into ARM CF

+                    IFNATIVE_BEFORE(NF_CF) {

+                        if(INVERTED_CARRY_BEFORE) {

+                            if(arm64_flagm)

+                                CFINV();

+                            else {

+                                MRS_nzcv(x3);

+                                EORx_mask(x3, x3, 1, 35, 0);  //mask=1<<NZCV_C

+                                MSR_nzcv(x3);

+                            }

+                        }

+                    } else {

+                        MRS_nzcv(x3);

+                        BFIx(x3, xFlags, 29, 1); // set C

+                        MSR_nzcv(x3);      // load CC into ARM CF

+                    }

                     IFX(X_CF) {

                         ADCSxw_REG(gd, gd, ed);

-                        CSETw(x3, cCS);

-                        BFIw(xFlags, x3, F_CF, 1);

+                        IFNATIVE(NF_CF) {} else {

+                            CSETw(x3, cCS);

+                            BFIw(xFlags, x3, F_CF, 1);

+                        }

                     } else {

                         ADCxw_REG(gd, gd, ed);

                     }