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| author | Leslie Zhai <zhaixiang@loongson.cn> | 2024-12-16 15:26:20 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-16 15:26:20 +0800 |
| commit | ed7dddc3d8732b5722690f5640e4a32962a6f667 (patch) | |
| tree | b4e5da14cb83fa47f23fa0d1b361cf5e03d44dfa /src | |
| parent | 4c6401c66b95f493f551ea373de164dfc48d020c (diff) | |
| download | box64-ed7dddc3d8732b5722690f5640e4a32962a6f667.tar.gz box64-ed7dddc3d8732b5722690f5640e4a32962a6f667.zip | |
[LA64_DYNAREC] Added PTEST opcode (#2158)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_660f.c | 34 | ||||
| -rw-r--r-- | src/dynarec/la64/la64_emitter.h | 1 |
2 files changed, 35 insertions, 0 deletions
diff --git a/src/dynarec/la64/dynarec_la64_660f.c b/src/dynarec/la64/dynarec_la64_660f.c index 3e8d3809..2037e460 100644 --- a/src/dynarec/la64/dynarec_la64_660f.c +++ b/src/dynarec/la64/dynarec_la64_660f.c @@ -346,6 +346,40 @@ uintptr_t dynarec64_660F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int XVSRLNI_H_W(v0, v0, 1); XVPERMI_D(q0, v0, 0b1000); break; + case 0x17: + INST_NAME("PTEST Gx, Ex"); + nextop = F8; + SETFLAGS(X_ALL, SF_SET); + GETGX(q0, 0); + GETEX(q1, 0, 0); + CLEAR_FLAGS(x3); + SET_DFNONE(); + v0 = fpu_get_scratch(dyn); + IFX (X_ZF) { + VAND_V(v0, q1, q0); + VSETEQZ_V(fcc0, v0); + BCEQZ_MARK(fcc0); + if (la64_lbt) { + ADDI_D(x3, xZR, 1 << F_ZF); + X64_SET_EFLAGS(x3, X_ZF); + } else { + ORI(xFlags, xFlags, 1 << F_ZF); + } + } + MARK; + IFX (X_CF) { + VANDN_V(v0, q0, q1); + VSETEQZ_V(fcc0, v0); + BCEQZ_MARK2(fcc0); + if (la64_lbt) { + ADDI_D(x3, xZR, 1 << F_CF); + X64_SET_EFLAGS(x3, X_CF); + } else { + ORI(xFlags, xFlags, 1 << F_CF); + } + } + MARK2; + break; case 0x1C: INST_NAME("PABSB Gx,Ex"); nextop = F8; diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h index 6e98806f..3cb2e4c5 100644 --- a/src/dynarec/la64/la64_emitter.h +++ b/src/dynarec/la64/la64_emitter.h @@ -1824,6 +1824,7 @@ LSX instruction starts with V, LASX instruction starts with XV. #define XVADDI_WU(vd, vj, imm5) EMIT(type_2RI5(0b01110110100010110, imm5, vj, vd)) #define XVSRLNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110111010000001, imm5, vj, vd)) #define XVSRLI_W(vd, vj, imm5) EMIT(type_2RI5(0b01110111001100001, imm5, vj, vd)) +#define VSETEQZ_V(cd, vj) EMIT(type_2R(0b0111001010011100100110, vj, cd & 0b111)) //////////////////////////////////////////////////////////////////////////////// // (undocumented) LBT extension instructions |