Fix build issues

3 files changed, 19 insertions, 29 deletions

diff --git a/src/dynarec/rv64/dynarec_rv64_helper.h b/src/dynarec/rv64/dynarec_rv64_helper.h
index 78a9cece..826e1822 100644
--- a/src/dynarec/rv64/dynarec_rv64_helper.h
+++ b/src/dynarec/rv64/dynarec_rv64_helper.h
@@ -34,43 +34,31 @@
 
 
 // Strong mem emulation helpers
-// Sequence of Read will trigger a DMB on "first" read if strongmem is 2
-// Squence of Write will trigger a DMB on "last" write if strongmem is 1
+#define SMREAD_MIN  2
+#define SMWRITE_MIN 1
+// Sequence of Read will trigger a DMB on "first" read if strongmem is >= SMREAD_MIN
+// Sequence of Write will trigger a DMB on "last" write if strongmem is >= 1
+// All Write operation that might use a lock all have a memory barrier if strongmem is >= SMWRITE_MIN
 // Opcode will read
-#define SMREAD() \
-    if (!dyn->smread && box64_dynarec_strongmem > 1) { SMDMB(); }
+#define SMREAD()    if((dyn->smread==0) && (box64_dynarec_strongmem>SMREAD_MIN)) {SMDMB();} else dyn->smread=1
 // Opcode will read with option forced lock
-#define SMREADLOCK(lock) \
-    if (lock || (!dyn->smread && box64_dynarec_strongmem > 1)) { SMDMB(); }
-// Opcode migh read (depend on nextop)
-#define SMMIGHTREAD() \
-    if (!MODREG) { SMREAD(); }
+#define SMREADLOCK(lock)    if((lock) || ((dyn->smread==0) && (box64_dynarec_strongmem>SMREAD_MIN))) {SMDMB();}
+// Opcode might read (depend on nextop)
+#define SMMIGHTREAD()   if(!MODREG) {SMREAD();}
 // Opcode has wrote
-#define SMWRITE() dyn->smwrite = 1
+#define SMWRITE()   dyn->smwrite=1
 // Opcode has wrote (strongmem>1 only)
-#define SMWRITE2() \
-    if (box64_dynarec_strongmem > 1) dyn->smwrite = 1
+#define SMWRITE2()   if(box64_dynarec_strongmem>SMREAD_MIN) dyn->smwrite=1
 // Opcode has wrote with option forced lock
-#define SMWRITELOCK(lock) \
-    if (lock) {           \
-        SMDMB();          \
-    } else                \
-        dyn->smwrite = 1
-// Opcode migh have wrote (depend on nextop)
-#define SMMIGHTWRITE() \
-    if (!MODREG) { SMWRITE(); }
+#define SMWRITELOCK(lock)   if(lock || (box64_dynarec_strongmem>SMWRITE_MIN /*&& (!ninst || dyn->smlastdmb!=ninst-1)*/)) {SMDMB();} else dyn->smwrite=1
+// Opcode might have wrote (depend on nextop)
+#define SMMIGHTWRITE()   if(!MODREG) {SMWRITE();}
 // Start of sequence
-#define SMSTART() SMEND()
+#define SMSTART()   SMEND()
 // End of sequence
-#define SMEND()                                               \
-    if (dyn->smwrite && box64_dynarec_strongmem) { FENCE(); } \
-    dyn->smwrite = 0;                                         \
-    dyn->smread = 0;
+#define SMEND()     if(dyn->smwrite && box64_dynarec_strongmem) {FENCE();} dyn->smwrite=0; dyn->smread=0;
 // Force a Data memory barrier (for LOCK: prefix)
-#define SMDMB()       \
-    FENCE();          \
-    dyn->smwrite = 0; \
-    dyn->smread = 1
+#define SMDMB()     FENCE(); dyn->smwrite=0; dyn->smread=1; dyn->smlastdmb = ninst
 
 // LOCK_* define
 #define LOCK_LOCK (int*)1
diff --git a/src/dynarec/rv64/dynarec_rv64_private.h b/src/dynarec/rv64/dynarec_rv64_private.h
index b7058c9a..c3274ded 100644
--- a/src/dynarec/rv64/dynarec_rv64_private.h
+++ b/src/dynarec/rv64/dynarec_rv64_private.h
@@ -118,6 +118,7 @@ typedef struct dynarec_rv64_s {
     size_t              insts_size; // size of the instruction size array (calculated)
     uint8_t             smread;    // for strongmem model emulation
     uint8_t             smwrite;    // for strongmem model emulation
+    uint32_t            smlastdmb;  // for strongmem model 3+
     uintptr_t           forward;    // address of the last end of code while testing forward
     uintptr_t           forward_to; // address of the next jump to (to check if everything is ok)
     int32_t             forward_size;   // size at the forward point
diff --git a/src/main.c b/src/main.c
index d0f01e2b..78fc7a78 100644
--- a/src/main.c
+++ b/src/main.c
@@ -77,6 +77,7 @@ int arm64_pmull = 0;
 int arm64_crc32 = 0;
 int arm64_atomics = 0;
 int arm64_flagm = 0;
+int arm64_flagm2 = 0;
 #elif defined(RV64)
 int rv64_zba = 0;
 int rv64_zbb = 0;