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authorptitSeb <sebastien.chev@gmail.com>2021-07-09 17:32:13 +0200
committerptitSeb <sebastien.chev@gmail.com>2021-07-09 17:32:13 +0200
commitf8ef852b4699dba4f8a7e76943a32b73b1e5d9f6 (patch)
tree12f12e7af3ae349759a8d7a39a229e4e72997b7a /src
parent741b03761abf3688893abb3bca279f039e4062c7 (diff)
downloadbox64-f8ef852b4699dba4f8a7e76943a32b73b1e5d9f6.tar.gz
box64-f8ef852b4699dba4f8a7e76943a32b73b1e5d9f6.zip
Added 66 0F C8..CF opcodes ([DYNAREC] too)
Diffstat (limited to 'src')
-rwxr-xr-xsrc/dynarec/arm64_emitter.h6
-rwxr-xr-xsrc/dynarec/dynarec_arm64_660f.c18
-rw-r--r--src/emu/x64run660f.c16
3 files changed, 38 insertions, 2 deletions
diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index 1ceee266..e6fe2fd6 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -628,9 +628,11 @@
 
 // REV
 #define REV_gen(sf, opc, Rn, Rd)        ((sf)<<31 | 1<<30 | 0b11010110<<21 | (opc)<<10 | (Rn)<<5 | (Rd))
-#define REVx(Rd, Rn)                    EMIT(REV_gen(1, 0b11, Rn, Rd))
-#define REVw(Rd, Rn)                    EMIT(REV_gen(0, 0b10, Rn, Rd))
+#define REV64x(Rd, Rn)                  EMIT(REV_gen(1, 0b11, Rn, Rd))
+#define REV32w(Rd, Rn)                  EMIT(REV_gen(0, 0b10, Rn, Rd))
 #define REVxw(Rd, Rn)                   EMIT(REV_gen(rex.w, 0b10|rex.w, Rn, Rd))
+#define REV16w(Rd, Rn)                  EMIT(REV_gen(0, 0b01, Rn, Rd))
+#define REV16x(Rd, Rn)                  EMIT(REV_gen(1, 0b01, Rn, Rd))
 
 // MRS
 #define MRS_gen(L, o0, op1, CRn, CRm, op2, Rt)  (0b1101010100<<22 | (L)<<21 | 1<<20 | (o0)<<19 | (op1)<<16 | (CRn)<<12 | (CRm)<<8 | (op2)<<5 | (Rt))
diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c
index 61afa927..0cddb61f 100755
--- a/src/dynarec/dynarec_arm64_660f.c
+++ b/src/dynarec/dynarec_arm64_660f.c
@@ -1344,6 +1344,24 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             }

             break;

 

+        case 0xC8:

+        case 0xC9:

+        case 0xCA:

+        case 0xCB:

+        case 0xCC:

+        case 0xCD:

+        case 0xCE:

+        case 0xCF:                  /* BSWAP reg */

+            INST_NAME("BSWAP Reg");

+            gd = xRAX+(opcode&7)+(rex.b<<3);

+            if(rex.w) {

+                REV64x(gd, gd);

+            } else {

+                REV16w(x1, gd);

+                BFIx(gd, x1, 0, 16);

+            }

+            break;

+

 

         case 0xD2:

             INST_NAME("PSRLD Gx,Ex");

diff --git a/src/emu/x64run660f.c b/src/emu/x64run660f.c
index 08f23f7d..94445359 100644
--- a/src/emu/x64run660f.c
+++ b/src/emu/x64run660f.c
@@ -1265,6 +1265,22 @@ int Run660F(x64emu_t *emu, rex_t rex)
         GX->q[1] = eax1.q[1];

         break;

 

+    case 0xC8:

+    case 0xC9:

+    case 0xCA:

+    case 0xCB:

+    case 0xCC:

+    case 0xCD:

+    case 0xCE:

+    case 0xCF:                  /* BSWAP reg16 */

+        tmp8u = (opcode&7)+(rex.b<<3);

+        if(rex.w) {

+            emu->regs[tmp8u].q[0] = __builtin_bswap64(emu->regs[tmp8u].q[0]);

+        } else {

+            emu->regs[tmp8u].word[0] = __builtin_bswap16(emu->regs[tmp8u].word[0]);

+        }

+        break;

+

     case 0xD1:  /* PSRLW Gx, Ex */

         nextop = F8;

         GETEX(0);