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authorptitSeb <sebastien.chev@gmail.com>2022-04-25 11:35:40 +0200
committerptitSeb <sebastien.chev@gmail.com>2022-04-25 11:35:40 +0200
commitfab4c72285fc7f0597d74fa80ef6863d257822b8 (patch)
tree999977e50335aea152e0eb969c1d20c96ad5b1ba /src
parent9bb42fc5bf70394780eaf5a7e43bde90e882fe73 (diff)
downloadbox64-fab4c72285fc7f0597d74fa80ef6863d257822b8.tar.gz
box64-fab4c72285fc7f0597d74fa80ef6863d257822b8.zip
[DYNAREC] Fixed some issue with XMM cache and Native calls (fixed Zoom title bitmap distortion)
Diffstat (limited to 'src')
-rwxr-xr-xsrc/dynarec/arm64/dynarec_arm64_helper.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.c b/src/dynarec/arm64/dynarec_arm64_helper.c
index f4067684..b444cde8 100755
--- a/src/dynarec/arm64/dynarec_arm64_helper.c
+++ b/src/dynarec/arm64/dynarec_arm64_helper.c
@@ -1227,10 +1227,10 @@ static void sse_purgecache(dynarec_arm_t* dyn, int ninst, int next, int s1)
                     ++old;
                 }
                 VSTR128_U12(dyn->n.ssecache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
-                if(!next) {
-                    fpu_free_reg(dyn, dyn->n.ssecache[i].reg);
-                    dyn->n.ssecache[i].v = -1;
-                }
+            }
+            if(!next) {
+                fpu_free_reg(dyn, dyn->n.ssecache[i].reg);
+                dyn->n.ssecache[i].v = -1;
             }
         }
     if(old!=-1) {
@@ -1250,16 +1250,16 @@ static void sse_reflectcache(dynarec_arm_t* dyn, int ninst, int s1)
 void fpu_pushcache(dynarec_arm_t* dyn, int ninst, int s1, int not07)
 {
     int start = not07?8:0;
-    // only SSE regs needs to be push back to xEmu
+    // only SSE regs needs to be push back to xEmu (needs to be "write")
     int n=0;
     for (int i=start; i<16; i++)
-        if(dyn->n.ssecache[i].v!=-1)
+        if((dyn->n.ssecache[i].v!=-1) && (dyn->n.ssecache[i].write))
             ++n;
     if(!n)
         return;
     MESSAGE(LOG_DUMP, "\tPush XMM Cache (%d)------\n", n);
     for (int i=start; i<16; ++i)
-        if(dyn->n.ssecache[i].v!=-1) {
+        if((dyn->n.ssecache[i].v!=-1) && (dyn->n.ssecache[i].write)) {
             VSTR128_U12(dyn->n.ssecache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
         }
     MESSAGE(LOG_DUMP, "\t------- Push XMM Cache (%d)\n", n);
@@ -1268,7 +1268,7 @@ void fpu_pushcache(dynarec_arm_t* dyn, int ninst, int s1, int not07)
 void fpu_popcache(dynarec_arm_t* dyn, int ninst, int s1, int not07)
 {
     int start = not07?8:0;
-    // only SSE regs needs to be pop back from xEmu
+    // only SSE regs needs to be pop back from xEmu (don't need to be "write" this time)
     int n=0;
     for (int i=start; i<16; i++)
         if(dyn->n.ssecache[i].v!=-1)