[DYNAREC] Added 0F C8..CF opcodes

3 files changed, 28 insertions, 1 deletions

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index 7511e28e..0d5bc7ff 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -565,6 +565,12 @@
 #define RBITw(Rd, Rn)                   EMIT(RBIT_gen(0, Rn, Rd))
 #define RBITxw(Rd, Rn)                  EMIT(RBIT_gen(rex.w, Rn, Rd))
 
+// REV
+#define REV_gen(sf, opc, Rn, Rd)        ((sf)<<31 | 1<<30 | 0b11010110<<21 | (opc)<<10 | (Rn)<<5 | (Rd))
+#define REVx(Rd, Rn)                    EMIT(REV_gen(1, 0b11, Rn, Rd))
+#define REVw(Rd, Rn)                    EMIT(REV_gen(0, 0b10, Rn, Rd))
+#define REVxw(Rd, Rn)                   EMIT(REV_gen(rex.w, 0b10|rex.w, Rn, Rd))
+
 // MRS
 #define MRS_gen(L, o0, op1, CRn, CRm, op2, Rt)  (0b1101010100<<22 | (L)<<21 | 1<<20 | (o0)<<19 | (op1)<<16 | (CRn)<<12 | (CRm)<<8 | (op2)<<5 | (Rt))
 // mrs    x0, nzcv : 1101010100 1 1 1 011 0100 0010 000 00000    o0=1(op0=3), op1=0b011(3) CRn=0b0100(4) CRm=0b0010(2) op2=0
diff --git a/src/dynarec/arm64_printer.c b/src/dynarec/arm64_printer.c
index a76dda64..6683695a 100755
--- a/src/dynarec/arm64_printer.c
+++ b/src/dynarec/arm64_printer.c
@@ -729,7 +729,15 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "RBIT %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn]);

         return buff;

     }

-

+    if(isMask(opcode, "f1011010110000000000oonnnnnddddd", &a)) {

+        if(!sf && option==2)

+            snprintf(buff, sizeof(buff), "REV %s, %s", Wt[Rd], Wt[Rn]);

+        else if (sf && option==3) 

+            snprintf(buff, sizeof(buff), "REV %s, %s", Xt[Rd], Xt[Rn]);

+        else

+            snprintf(buff, sizeof(buff), "REV%d %s, %s", 8<<option, sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn]);

+        return buff;

+    }

 

     // MULL ADD

     if(isMask(opcode, "10011011U01mmmmm0aaaaannnnnddddd", &a)) {

diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c
index 94966bf5..25ffec7e 100755
--- a/src/dynarec/dynarec_arm64_0f.c
+++ b/src/dynarec/dynarec_arm64_0f.c
@@ -742,6 +742,19 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             VMOVQ(v0, d0);

             break;

 

+        case 0xC8:

+        case 0xC9:

+        case 0xCA:

+        case 0xCB:

+        case 0xCC:

+        case 0xCD:

+        case 0xCE:

+        case 0xCF:                  /* BSWAP reg */

+            INST_NAME("BSWAP Reg");

+            gd = xRAX+(opcode&7)+(rex.b<<3);

+            REVxw(gd, gd);

+            break;

+

         default:

             DEFAULT;

     }