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authorYang Liu <numbksco@gmail.com>2024-03-06 00:59:15 +0800
committerGitHub <noreply@github.com>2024-03-05 17:59:15 +0100
commitfedb8bd816b142a1c48d3a073fadca93a5658195 (patch)
treeacbaa97f589cc1997fb80743c3e23364cbb2d973 /src
parentc3f97dd73053e2c5341785f80c345ca4f972d927 (diff)
downloadbox64-fedb8bd816b142a1c48d3a073fadca93a5658195.tar.gz
box64-fedb8bd816b142a1c48d3a073fadca93a5658195.zip
[LA64_DYNAREC] Added more opcodes and more instructions in emitter and printer (#1332)
Diffstat (limited to 'src')
-rw-r--r--src/dynarec/la64/dynarec_la64_00.c42
-rw-r--r--src/dynarec/la64/la64_emitter.h5
-rw-r--r--src/dynarec/la64/la64_printer.c10
3 files changed, 57 insertions, 0 deletions
diff --git a/src/dynarec/la64/dynarec_la64_00.c b/src/dynarec/la64/dynarec_la64_00.c
index 2417ad18..8ad4a9d4 100644
--- a/src/dynarec/la64/dynarec_la64_00.c
+++ b/src/dynarec/la64/dynarec_la64_00.c
@@ -486,6 +486,39 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
             GETED(0);
             emit_test32(dyn, ninst, rex, ed, gd, x3, x4, x5);
             break;
+        case 0x88:
+            INST_NAME("MOV Eb, Gb");
+            nextop = F8;
+            gd = ((nextop & 0x38) >> 3) + (rex.r << 3);
+            if (rex.rex) {
+                gb2 = 0;
+                gb1 = TO_LA64(gd);
+            } else {
+                gb2 = ((gd & 4) << 1);
+                gb1 = TO_LA64(gd & 3);
+            }
+            if (gb2) {
+                gd = x4;
+                BSTRPICK_D(gd, gb1, gb2 + 7, gb2);
+            } else {
+                gd = gb1; // no need to extract
+            }
+            if (MODREG) {
+                ed = (nextop & 7) + (rex.b << 3);
+                if (rex.rex) {
+                    eb1 = TO_LA64(ed);
+                    eb2 = 0;
+                } else {
+                    eb1 = TO_LA64(ed & 3); // Ax, Cx, Dx or Bx
+                    eb2 = ((ed & 4) >> 2); // L or H
+                }
+                BSTRINS_D(eb1, gd, eb2 * 8 + 7, eb2 * 8);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, &lock, 1, 0);
+                ST_B(gb1, ed, fixedaddress);
+                SMWRITELOCK(lock);
+            }
+            break;
         case 0x89:
             INST_NAME("MOV Ed, Gd");
             nextop = F8;
@@ -546,6 +579,15 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
                 MVxw(gd, x2);
             }
             break;
+        case 0x98:
+            INST_NAME("CWDE");
+            if (rex.w) {
+                SEXT_W(xRAX, xRAX);
+            } else {
+                EXT_W_H(xRAX, xRAX);
+                ZEROUP(xRAX);
+            }
+            break;
         case 0xA8:
             INST_NAME("TEST AL, Ib");
             SETFLAGS(X_ALL, SF_SET_PENDING);
diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h
index 3089a729..b8c72ee7 100644
--- a/src/dynarec/la64/la64_emitter.h
+++ b/src/dynarec/la64/la64_emitter.h
@@ -492,6 +492,11 @@ f24-f31  fs0-fs7   Static registers                Callee
 // MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
 #define ST_D(rd, rj, imm12) EMIT(type_2RI12(0b0010100111, imm12, rj, rd))
 
+// GR[rd] = SignExtend(GR[rj][15:0], GRLEN)
+#define EXT_W_H(rd, rj) EMIT(type_2R(0b10110, rj, rd))
+// GR[rd] = SignExtend(GR[rj][7:0], GRLEN)
+#define EXT_W_B(rd, rj) EMIT(type_2R(0b10111, rj, rd))
+
 ////////////////////////////////////////////////////////////////////////////////
 // LBT extension instructions
 
diff --git a/src/dynarec/la64/la64_printer.c b/src/dynarec/la64/la64_printer.c
index 075842fb..bacecfb8 100644
--- a/src/dynarec/la64/la64_printer.c
+++ b/src/dynarec/la64/la64_printer.c
@@ -450,6 +450,16 @@ const char* la64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "%-15s %s, %s, %d", "ST.D", Xt[Rd], Xt[Rj], signExtend(imm, 12));
         return buff;
     }
+    // EXT.W.H
+    if(isMask(opcode, "0000000000000000010110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "EXT.W.H", Xt[Rd], Xt[Rj]);
+        return buff;
+    }
+    // EXT.W.B
+    if(isMask(opcode, "0000000000000000010111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "EXT.W.B", Xt[Rd], Xt[Rj]);
+        return buff;
+    }
     // X64CLRSM
     if(isMask(opcode, "00000000000000001000000000101000", &a)) {
         snprintf(buff, sizeof(buff), "X64CLRSM");