diff options
Diffstat (limited to 'src/dynarec')
| -rw-r--r-- | src/dynarec/arm64/arm64_emitter.h | 7 | ||||
| -rw-r--r-- | src/dynarec/arm64/dynarec_arm64_helper.h | 9 |
2 files changed, 15 insertions, 1 deletions
diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h index ae337ac6..a4269283 100644 --- a/src/dynarec/arm64/arm64_emitter.h +++ b/src/dynarec/arm64/arm64_emitter.h @@ -489,12 +489,19 @@ int convert_bitmask(uint64_t bitmask); // Data Memory Barrier #define DMB_gen(CRm) (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b01<<5 | 0b11111) #define DMB_ISH() EMIT(DMB_gen(0b1011)) +#define DMB_ISHLD() EMIT(DMB_gen(0b1001)) +#define DMB_ISHST() EMIT(DMB_gen(0b1010)) +#define DMB_LD() EMIT(DMB_gen(0b1101)) +#define DMB_ST() EMIT(DMB_gen(0b1110)) #define DMB_SY() EMIT(DMB_gen(0b1111)) // Data Synchronization Barrier #define DSB_gen(CRm) (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b00<<5 | 0b11111) #define DSB_ISH() EMIT(DSB_gen(0b1011)) +#define DSB_ISHLD() EMIT(DSB_gen(0b1001)) #define DSB_ISHST() EMIT(DSB_gen(0b1010)) +#define DSB_LD() EMIT(DSB_gen(0b1101)) +#define DSB_ST() EMIT(DSB_gen(0b1110)) #define DSB_SY() EMIT(DSB_gen(0b1111)) // Break diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h index cae4add9..5b4e5c1d 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.h +++ b/src/dynarec/arm64/dynarec_arm64_helper.h @@ -85,7 +85,14 @@ // End of sequence #define SMEND() if(dyn->smwrite && box64_dynarec_strongmem && (box64_dynarec_strongmem!=SMREAD_VAL)) {DMB_ISH();} dyn->smwrite=0; dyn->smread=0 // Force a Data memory barrier (for LOCK: prefix) -#define SMDMB() if(box64_dynarec_strongmem){DSB_ISH();}else{DMB_ISH();} dyn->smwrite=0; dyn->smread=0 +#define SMDMB() \ + if (box64_dynarec_strongmem && !box64_dynarec_weakbarrier) { \ + DSB_ISH(); \ + } else { \ + DMB_ISH(); \ + } \ + dyn->smwrite = 0; \ + dyn->smread = 0 #endif |