diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_00.c | 8 | ||||
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_emit_shift.c | 107 | ||||
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_f20f.c | 24 | ||||
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_helper.h | 2 | ||||
| -rw-r--r-- | src/dynarec/la64/la64_emitter.h | 1392 |
5 files changed, 811 insertions, 722 deletions
diff --git a/src/dynarec/la64/dynarec_la64_00.c b/src/dynarec/la64/dynarec_la64_00.c index e27f2acf..0aa9a65d 100644 --- a/src/dynarec/la64/dynarec_la64_00.c +++ b/src/dynarec/la64/dynarec_la64_00.c @@ -1719,6 +1719,14 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni WBACK; if (!wback && !rex.w) ZEROUP(ed); break; + case 1: + INST_NAME("ROR Ed, CL"); + SETFLAGS(X_OF | X_CF, SF_SUBSET); + GETED(0); + emit_ror32(dyn, ninst, rex, ed, xRCX, x3, x4); + WBACK; + if (!wback && !rex.w) ZEROUP(ed); + break; case 4: case 6: INST_NAME("SHL Ed, CL"); diff --git a/src/dynarec/la64/dynarec_la64_emit_shift.c b/src/dynarec/la64/dynarec_la64_emit_shift.c index 7cc978a7..291674eb 100644 --- a/src/dynarec/la64/dynarec_la64_emit_shift.c +++ b/src/dynarec/la64/dynarec_la64_emit_shift.c @@ -659,13 +659,11 @@ void emit_ror32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, return; } - if (la64_lbt) { - IFX (X_ALL) { - if (rex.w) - X64_ROTRI_D(s1, c); - else - X64_ROTRI_W(s1, c); - } + IFXA ((X_CF | X_OF), la64_lbt) { + if (rex.w) + X64_ROTRI_D(s1, c); + else + X64_ROTRI_W(s1, c); } ROTRIxw(s1, s1, c); @@ -676,7 +674,10 @@ void emit_ror32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, if (la64_lbt) return; - CLEAR_FLAGS(s3); + IFX (X_CF | X_OF) { + MOV64x(s4, ((1UL << F_CF) | (1UL << F_OF))); + ANDN(xFlags, xFlags, s4); + } IFX (X_CF) { SRLIxw(s3, s1, rex.w ? 63 : 31); OR(xFlags, xFlags, s3); @@ -706,13 +707,11 @@ void emit_rol32(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s SET_DFNONE(); } - if (la64_lbt) { - IFX (X_ALL) { - if (rex.w) - X64_ROTL_D(s1, s2); - else - X64_ROTL_W(s1, s2); - } + IFXA ((X_CF | X_OF), la64_lbt) { + if (rex.w) + X64_ROTL_D(s1, s2); + else + X64_ROTL_W(s1, s2); } if (rex.w) { @@ -736,7 +735,10 @@ void emit_rol32(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s if (la64_lbt) return; - CLEAR_FLAGS(s3); + IFX (X_CF | X_OF) { + MOV64x(s4, ((1UL << F_CF) | (1UL << F_OF))); + ANDN(xFlags, xFlags, s4); + } IFX (X_CF | X_OF) { ANDI(s4, s1, 1); // LSB == F_CF IFX (X_CF) OR(xFlags, xFlags, s4); @@ -752,6 +754,65 @@ void emit_rol32(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s } } +// emit ROR32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch +void emit_ror32(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4) +{ + int64_t j64; + + if (rex.w) { + ANDI(s4, s2, 0x3f); + } else { + ANDI(s4, s2, 0x1f); + ZEROUP(s1); + } + BEQ_NEXT(s4, xZR); + IFX (X_PEND) { + SDxw(s2, xEmu, offsetof(x64emu_t, op2)); + SET_DF(s4, rex.w ? d_ror64 : d_ror32); + } else IFX (X_ALL) { + SET_DFNONE(); + } + + IFXA ((X_CF | X_OF), la64_lbt) { + if (rex.w) + X64_ROTR_D(s1, s4); + else + X64_ROTR_W(s1, s4); + } + + if (rex.w) { + ROTR_D(s1, s1, s4); + } else { + ROTR_W(s1, s1, s4); + } + + IFX (X_PEND) { + SDxw(s1, xEmu, offsetof(x64emu_t, res)); + } + + if (la64_lbt) return; + + IFX (X_CF | X_OF) { + MOV64x(s4, ((1UL << F_CF) | (1UL << F_OF))); + ANDN(xFlags, xFlags, s4); + } + IFX (X_CF) { + SRLIxw(s3, s1, rex.w ? 63 : 31); + OR(xFlags, xFlags, s3); + } + IFX (X_OF) { + // the OF flag is set to the exclusive OR of the two most-significant bits of the result + ADDI_D(s3, xZR, 1); + BNE_NEXT(s2, s3); + SRLIxw(s3, s1, rex.w ? 63 : 31); + SRLIxw(s4, s1, rex.w ? 62 : 30); + XOR(s3, s3, s4); + ANDI(s3, s3, 1); + SLLI_D(s3, s3, F_OF); + OR(xFlags, xFlags, s3); + } +} + // emit ROL32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch void emit_rol32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4) @@ -772,13 +833,11 @@ void emit_rol32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, return; } - if (la64_lbt) { - IFX (X_CF | X_OF) { - if (rex.w) - X64_ROTLI_D(s1, c); - else - X64_ROTLI_W(s1, c); - } + IFXA ((X_CF | X_OF), la64_lbt) { + if (rex.w) + X64_ROTLI_D(s1, c); + else + X64_ROTLI_W(s1, c); } ROTRIxw(s1, s1, (rex.w ? 64 : 32) - c); @@ -792,7 +851,7 @@ void emit_rol32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, if (la64_lbt) return; IFX (X_CF | X_OF) { - MOV64x(s3, (1UL << F_CF | 1UL << F_OF)); + MOV64x(s3, ((1UL << F_CF) | (1UL << F_OF))); ANDN(xFlags, xFlags, s3); } IFX (X_CF | X_OF) { diff --git a/src/dynarec/la64/dynarec_la64_f20f.c b/src/dynarec/la64/dynarec_la64_f20f.c index 9bbd6ff7..9f8bcc24 100644 --- a/src/dynarec/la64/dynarec_la64_f20f.c +++ b/src/dynarec/la64/dynarec_la64_f20f.c @@ -24,7 +24,8 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog) { - (void)ip; (void)need_epilog; + (void)ip; + (void)need_epilog; uint8_t opcode = F8; uint8_t nextop; @@ -44,12 +45,12 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int MAYUSE(v0); MAYUSE(v1); - switch(opcode) { + switch (opcode) { case 0x10: INST_NAME("MOVSD Gx, Ex"); nextop = F8; GETG; - if(MODREG) { + if (MODREG) { ed = (nextop & 7) + (rex.b << 3); v0 = sse_get_reg(dyn, ninst, x1, gd, 1); v1 = sse_get_reg(dyn, ninst, x1, ed, 0); @@ -68,7 +69,7 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int nextop = F8; GETG; v0 = sse_get_reg(dyn, ninst, x1, gd, 0); - if(MODREG) { + if (MODREG) { ed = (nextop & 7) + (rex.b << 3); d0 = sse_get_reg(dyn, ninst, x1, ed, 0); VEXTRINS_D(d0, v0, 0); // d0[63:0] = v0[63:0] @@ -78,6 +79,21 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int SMWRITE2(); } break; + case 0x12: + INST_NAME("MOVDDUP Gx, Ex"); + nextop = F8; + GETG; + if (MODREG) { + d0 = sse_get_reg(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0); + v0 = sse_get_reg_empty(dyn, ninst, x1, gd); + VREPLVE_D(v0, d0, xZR); + } else { + SMREAD(); + v0 = sse_get_reg_empty(dyn, ninst, x1, gd); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 0, 0); + VLDREPL_D(v0, ed, 0); + } + break; case 0x2A: INST_NAME("CVTSI2SD Gx, Ed"); nextop = F8; diff --git a/src/dynarec/la64/dynarec_la64_helper.h b/src/dynarec/la64/dynarec_la64_helper.h index f2972274..9bf58812 100644 --- a/src/dynarec/la64/dynarec_la64_helper.h +++ b/src/dynarec/la64/dynarec_la64_helper.h @@ -848,6 +848,7 @@ void* la64_next(x64emu_t* emu, uintptr_t addr); #define emit_sar32c STEPNAME(emit_sar32c) #define emit_shld32c STEPNAME(emit_shld32c) #define emit_shrd32c STEPNAME(emit_shrd32c) +#define emit_ror32 STEPNAME(emit_ror32) #define emit_ror32c STEPNAME(emit_ror32c) #define emit_rol32 STEPNAME(emit_rol32) #define emit_rol32c STEPNAME(emit_rol32c) @@ -949,6 +950,7 @@ void emit_sar16(dynarec_la64_t* dyn, int ninst, int s1, int s2, int s3, int s4, void emit_sar32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4); void emit_shld32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, uint32_t c, int s3, int s4); void emit_shrd32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, uint32_t c, int s3, int s4); +void emit_ror32(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4); void emit_ror32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4); void emit_rol32(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4); void emit_rol32c(dynarec_la64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4); diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h index dc06d2a3..5f34cd14 100644 --- a/src/dynarec/la64/la64_emitter.h +++ b/src/dynarec/la64/la64_emitter.h @@ -33,67 +33,67 @@ f24-f31 fs0-fs7 Static registers Callee ip in r20 */ // x86 Register mapping -#define xRAX 12 -#define xRCX 13 -#define xRDX 14 -#define xRBX 15 -#define xRSP 16 -#define xRBP 17 -#define xRSI 18 -#define xRDI 19 -#define xR8 23 -#define xR9 24 -#define xR10 25 -#define xR11 26 -#define xR12 27 -#define xR13 28 -#define xR14 29 -#define xR15 30 -#define xFlags 31 -#define xRIP 20 +#define xRAX 12 +#define xRCX 13 +#define xRDX 14 +#define xRBX 15 +#define xRSP 16 +#define xRBP 17 +#define xRSI 18 +#define xRDI 19 +#define xR8 23 +#define xR9 24 +#define xR10 25 +#define xR11 26 +#define xR12 27 +#define xR13 28 +#define xR14 29 +#define xR15 30 +#define xFlags 31 +#define xRIP 20 #define xSavedSP 22 // function to move from x86 regs number to LA64 reg number -#define TO_LA64(A) (((A)>7)?((A)+15):((A)+12)) +#define TO_LA64(A) (((A) > 7) ? ((A) + 15) : ((A) + 12)) // 32bits version -#define wEAX xRAX -#define wECX xRCX -#define wEDX xRDX -#define wEBX xRBX -#define wESP xRSP -#define wEBP xRBP -#define wESI xRSI -#define wEDI xRDI -#define wR8 xR8 -#define wR9 xR9 -#define wR10 xR10 -#define wR11 xR11 -#define wR12 xR12 -#define wR13 xR13 -#define wR14 xR14 -#define wR15 xR15 -#define wFlags xFlags +#define wEAX xRAX +#define wECX xRCX +#define wEDX xRDX +#define wEBX xRBX +#define wESP xRSP +#define wEBP xRBP +#define wESI xRSI +#define wEDI xRDI +#define wR8 xR8 +#define wR9 xR9 +#define wR10 xR10 +#define wR11 xR11 +#define wR12 xR12 +#define wR13 xR13 +#define wR14 xR14 +#define wR15 xR15 +#define wFlags xFlags // scratch registers -#define x1 5 -#define x2 6 -#define x3 7 -#define x4 8 -#define x5 9 -#define x6 10 -#define x7 11 +#define x1 5 +#define x2 6 +#define x3 7 +#define x4 8 +#define x5 9 +#define x6 10 +#define x7 11 // 32bits version of scratch -#define w1 x1 -#define w2 x2 -#define w3 x3 -#define w4 x4 -#define w5 x5 -#define w6 x6 +#define w1 x1 +#define w2 x2 +#define w3 x3 +#define w4 x4 +#define w5 x5 +#define w6 x6 // emu is r0 -#define xEmu 4 +#define xEmu 4 // LA64 RA -#define xRA 1 -#define ra xRA +#define xRA 1 +#define ra xRA // LA64 SP -#define xSP 3 +#define xSP 3 // RV64 args #define A0 4 #define A1 5 @@ -104,9 +104,9 @@ f24-f31 fs0-fs7 Static registers Callee #define A6 10 #define A7 11 // xZR regs -#define xZR 0 -#define wZR xZR -#define r0 xZR +#define xZR 0 +#define wZR xZR +#define r0 xZR #define fcc0 0 #define fcc1 1 @@ -175,14 +175,17 @@ f24-f31 fs0-fs7 Static registers Callee #define type_I26(opc, imm26) ((opc) << 26 | ((imm26) & 0xFFFF) << 10 | ((imm26 >> 16) & 0x3FF)) // Made-up formats not found in the spec. -#define type_1RI13(opc, imm13, rd) ((opc) << 18 | ((imm13) & 0x1FFFF) << 5 | (rd)) -#define type_2RI1(opc, imm1, rj, rd) ((opc) << 11 | ((imm1) & 0x1) << 10 | (rj) << 5 | (rd)) -#define type_2RI2(opc, imm2, rj, rd) ((opc) << 12 | ((imm2) & 0x3) << 10 | (rj) << 5 | (rd)) -#define type_2RI3(opc, imm3, rj, rd) ((opc) << 13 | ((imm3) & 0x7 ) << 10 | (rj) << 5 | (rd)) -#define type_2RI4(opc, imm4, rj, rd) ((opc) << 14 | ((imm4) & 0xF ) << 10 | (rj) << 5 | (rd)) -#define type_2RI5(opc, imm5, rj, rd) ((opc) << 15 | ((imm5) & 0x1F) << 10 | (rj) << 5 | (rd)) -#define type_2RI6(opc, imm6, rj, rd) ((opc) << 16 | ((imm6) & 0x3F) << 10 | (rj) << 5 | (rd)) -#define type_2RI7(opc, imm7, rj, rd) ((opc) << 17 | ((imm7) & 0x7F) << 10 | (rj) << 5 | (rd)) +#define type_1RI13(opc, imm13, rd) ((opc) << 18 | ((imm13) & 0x1FFFF) << 5 | (rd)) +#define type_2RI1(opc, imm1, rj, rd) ((opc) << 11 | ((imm1) & 0x1) << 10 | (rj) << 5 | (rd)) +#define type_2RI2(opc, imm2, rj, rd) ((opc) << 12 | ((imm2) & 0x3) << 10 | (rj) << 5 | (rd)) +#define type_2RI3(opc, imm3, rj, rd) ((opc) << 13 | ((imm3) & 0x7) << 10 | (rj) << 5 | (rd)) +#define type_2RI4(opc, imm4, rj, rd) ((opc) << 14 | ((imm4) & 0xF) << 10 | (rj) << 5 | (rd)) +#define type_2RI5(opc, imm5, rj, rd) ((opc) << 15 | ((imm5) & 0x1F) << 10 | (rj) << 5 | (rd)) +#define type_2RI6(opc, imm6, rj, rd) ((opc) << 16 | ((imm6) & 0x3F) << 10 | (rj) << 5 | (rd)) +#define type_2RI7(opc, imm7, rj, rd) ((opc) << 17 | ((imm7) & 0x7F) << 10 | (rj) << 5 | (rd)) +#define type_2RI9(opc, imm9, rj, rd) ((opc) << 19 | ((imm9) & 0x1FF) << 10 | (rj) << 5 | (rd)) +#define type_2RI10(opc, imm10, rj, rd) ((opc) << 20 | ((imm10) & 0x3FF) << 10 | (rj) << 5 | (rd)) +#define type_2RI11(opc, imm11, rj, rd) ((opc) << 21 | ((imm11) & 0x7FF) << 10 | (rj) << 5 | (rd)) // tmp = GR[rj][31:0] + GR[rk][31:0] // Gr[rd] = SignExtend(tmp[31:0], GRLEN) @@ -549,42 +552,42 @@ f24-f31 fs0-fs7 Static registers Callee // if GR[rj] == GR[rd]: // PC = PC + SignExtend({imm16, 2'b0}, GRLEN) -#define BEQ(rj, rd, imm18) EMIT(type_2RI16(0b010110, ((imm18)>>2), rj, rd)) +#define BEQ(rj, rd, imm18) EMIT(type_2RI16(0b010110, ((imm18) >> 2), rj, rd)) // if GR[rj] != GR[rd]: // PC = PC + SignExtend({imm16, 2'b0}, GRLEN) -#define BNE(rj, rd, imm18) EMIT(type_2RI16(0b010111, ((imm18)>>2), rj, rd)) +#define BNE(rj, rd, imm18) EMIT(type_2RI16(0b010111, ((imm18) >> 2), rj, rd)) // if signed(GR[rj]) < signed(GR[rd]): // PC = PC + SignExtend({imm16, 2'b0}, GRLEN) -#define BLT(rj, rd, imm18) EMIT(type_2RI16(0b011000, ((imm18)>>2), rj, rd)) +#define BLT(rj, rd, imm18) EMIT(type_2RI16(0b011000, ((imm18) >> 2), rj, rd)) // if signed(GR[rj]) >= signed(GR[rd]): // PC = PC + SignExtend({imm16, 2'b0}, GRLEN) -#define BGE(rj, rd, imm18) EMIT(type_2RI16(0b011001, ((imm18)>>2), rj, rd)) +#define BGE(rj, rd, imm18) EMIT(type_2RI16(0b011001, ((imm18) >> 2), rj, rd)) // if unsigned(GR[rj]) == unsigned(GR[rd]): // PC = PC + SignExtend({imm16, 2'b0}, GRLEN) -#define BLTU(rj, rd, imm18) EMIT(type_2RI16(0b011010, ((imm18)>>2), rj, rd)) +#define BLTU(rj, rd, imm18) EMIT(type_2RI16(0b011010, ((imm18) >> 2), rj, rd)) // if unsigned(GR[rj]) == unsigned(GR[rd]): // PC = PC + SignExtend({imm16, 2'b0}, GRLEN) -#define BGEU(rj, rd, imm18) EMIT(type_2RI16(0b011011, ((imm18)>>2), rj, rd)) +#define BGEU(rj, rd, imm18) EMIT(type_2RI16(0b011011, ((imm18) >> 2), rj, rd)) // if GR[rj] == 0: // PC = PC + SignExtend({imm21, 2'b0}, GRLEN) -#define BEQZ(rj, imm23) EMIT(type_1RI21(0b010000, ((imm23)>>2), rj)) +#define BEQZ(rj, imm23) EMIT(type_1RI21(0b010000, ((imm23) >> 2), rj)) // if GR[rj] != 0: // PC = PC + SignExtend({imm21, 2'b0}, GRLEN) #define BNEZ(rj, imm23) EMIT(type_1RI21(0b010001, ((imm23) >> 2), rj)) -#define BCEQZ(cj, imm23) EMIT(type_1RI21(0b010010, ((imm23)>>2), 0b00000 | cj)) -#define BCNEZ(cj, imm23) EMIT(type_1RI21(0b010010, ((imm23)>>2), 0b01000 | cj)) +#define BCEQZ(cj, imm23) EMIT(type_1RI21(0b010010, ((imm23) >> 2), 0b00000 | cj)) +#define BCNEZ(cj, imm23) EMIT(type_1RI21(0b010010, ((imm23) >> 2), 0b01000 | cj)) // GR[rd] = PC + 4 // PC = GR[rj] + SignExtend({imm16, 2'b0}, GRLEN) -#define JIRL(rd, rj, imm18) EMIT(type_2RI16(0b010011, ((imm18)>>2), rj, rd)) +#define JIRL(rd, rj, imm18) EMIT(type_2RI16(0b010011, ((imm18) >> 2), rj, rd)) // PC = GR[rj] #define BR(rj) JIRL(xZR, rj, 0x0) // PC = PC + SignExtend({imm26, 2'b0}, GRLEN) -#define B(imm28) EMIT(type_I26(0b010100, ((imm28)>>2))) +#define B(imm28) EMIT(type_I26(0b010100, ((imm28) >> 2))) #define B__(reg1, reg2, imm28) B(imm28) #define BEQ_safe(rj, rd, imm) \ @@ -921,519 +924,521 @@ LSX instruction starts with V, LASX instruction starts with XV. */ -#define VADD_B(vd, vj, vk) EMIT(type_3R(0b01110000000010100, vk, vj, vd)) -#define VADD_H(vd, vj, vk) EMIT(type_3R(0b01110000000010101, vk, vj, vd)) -#define VADD_W(vd, vj, vk) EMIT(type_3R(0b01110000000010110, vk, vj, vd)) -#define VADD_D(vd, vj, vk) EMIT(type_3R(0b01110000000010111, vk, vj, vd)) -#define VADD_Q(vd, vj, vk) EMIT(type_3R(0b01110001001011010, vk, vj, vd)) -#define VSUB_B(vd, vj, vk) EMIT(type_3R(0b01110000000011000, vk, vj, vd)) -#define VSUB_H(vd, vj, vk) EMIT(type_3R(0b01110000000011001, vk, vj, vd)) -#define VSUB_W(vd, vj, vk) EMIT(type_3R(0b01110000000011010, vk, vj, vd)) -#define VSUB_D(vd, vj, vk) EMIT(type_3R(0b01110000000011011, vk, vj, vd)) -#define VSUB_Q(vd, vj, vk) EMIT(type_3R(0b01110001001011011, vk, vj, vd)) -#define VADDI_BU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010100, imm5, vj, vd)) -#define VADDI_HU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010101, imm5, vj, vd)) -#define VADDI_WU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010110, imm5, vj, vd)) -#define VADDI_DU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010111, imm5, vj, vd)) -#define VSUBI_BU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011000, imm5, vj, vd)) -#define VSUBI_HU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011001, imm5, vj, vd)) -#define VSUBI_WU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011010, imm5, vj, vd)) -#define VSUBI_DU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011011, imm5, vj, vd)) -#define VSADD_B(vd, vj, vk) EMIT(type_3R(0b01110000010001100, vk, vj, vd)) -#define VSADD_H(vd, vj, vk) EMIT(type_3R(0b01110000010001101, vk, vj, vd)) -#define VSADD_W(vd, vj, vk) EMIT(type_3R(0b01110000010001110, vk, vj, vd)) -#define VSADD_D(vd, vj, vk) EMIT(type_3R(0b01110000010001111, vk, vj, vd)) -#define VSADD_BU(vd, vj, vk) EMIT(type_3R(0b01110000010010100, vk, vj, vd)) -#define VSADD_HU(vd, vj, vk) EMIT(type_3R(0b01110000010010101, vk, vj, vd)) -#define VSADD_WU(vd, vj, vk) EMIT(type_3R(0b01110000010010110, vk, vj, vd)) -#define VSADD_DU(vd, vj, vk) EMIT(type_3R(0b01110000010010111, vk, vj, vd)) -#define VSSUB_B(vd, vj, vk) EMIT(type_3R(0b01110000010010000, vk, vj, vd)) -#define VSSUB_H(vd, vj, vk) EMIT(type_3R(0b01110000010010001, vk, vj, vd)) -#define VSSUB_W(vd, vj, vk) EMIT(type_3R(0b01110000010010010, vk, vj, vd)) -#define VSSUB_D(vd, vj, vk) EMIT(type_3R(0b01110000010010011, vk, vj, vd)) -#define VSSUB_BU(vd, vj, vk) EMIT(type_3R(0b01110000010011000, vk, vj, vd)) -#define VSSUB_HU(vd, vj, vk) EMIT(type_3R(0b01110000010011001, vk, vj, vd)) -#define VSSUB_WU(vd, vj, vk) EMIT(type_3R(0b01110000010011010, vk, vj, vd)) -#define VSSUB_DU(vd, vj, vk) EMIT(type_3R(0b01110000010011011, vk, vj, vd)) -#define VHADDW_H_B(vd, vj, vk) EMIT(type_3R(0b01110000010101000, vk, vj, vd)) -#define VHADDW_W_H(vd, vj, vk) EMIT(type_3R(0b01110000010101001, vk, vj, vd)) -#define VHADDW_D_W(vd, vj, vk) EMIT(type_3R(0b01110000010101010, vk, vj, vd)) -#define VHADDW_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000010101011, vk, vj, vd)) -#define VHADDW_HU_BU(vd, vj, vk) EMIT(type_3R(0b01110000010110000, vk, vj, vd)) -#define VHADDW_WU_HU(vd, vj, vk) EMIT(type_3R(0b01110000010110001, vk, vj, vd)) -#define VHADDW_DU_WU(vd, vj, vk) EMIT(type_3R(0b01110000010110010, vk, vj, vd)) -#define VHADDW_QU_DU(vd, vj, vk) EMIT(type_3R(0b01110000010110011, vk, vj, vd)) -#define VHSUBW_H_B(vd, vj, vk) EMIT(type_3R(0b01110000010101100, vk, vj, vd)) -#define VHSUBW_W_H(vd, vj, vk) EMIT(type_3R(0b01110000010101101, vk, vj, vd)) -#define VHSUBW_D_W(vd, vj, vk) EMIT(type_3R(0b01110000010101110, vk, vj, vd)) -#define VHSUBW_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000010101111, vk, vj, vd)) -#define VHSUBW_HU_BU(vd, vj, vk) EMIT(type_3R(0b01110000010110100, vk, vj, vd)) -#define VHSUBW_WU_HU(vd, vj, vk) EMIT(type_3R(0b01110000010110101, vk, vj, vd)) -#define VHSUBW_DU_WU(vd, vj, vk) EMIT(type_3R(0b01110000010110110, vk, vj, vd)) -#define VHSUBW_QU_DU(vd, vj, vk) EMIT(type_3R(0b01110000010110111, vk, vj, vd)) -#define VADDWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000000111100, vk, vj, vd)) -#define VADDWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000000111101, vk, vj, vd)) -#define VADDWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000000111110, vk, vj, vd)) -#define VADDWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000000111111, vk, vj, vd)) -#define VADDWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000001000100, vk, vj, vd)) -#define VADDWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000001000101, vk, vj, vd)) -#define VADDWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000001000110, vk, vj, vd)) -#define VADDWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000001000111, vk, vj, vd)) -#define VSUBWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000001000000, vk, vj, vd)) -#define VSUBWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000001000001, vk, vj, vd)) -#define VSUBWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000001000010, vk, vj, vd)) -#define VSUBWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000001000011, vk, vj, vd)) -#define VSUBWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000001001000, vk, vj, vd)) -#define VSUBWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000001001001, vk, vj, vd)) -#define VSUBWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000001001010, vk, vj, vd)) -#define VSUBWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000001001011, vk, vj, vd)) -#define VADDWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001011100, vk, vj, vd)) -#define VADDWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001011101, vk, vj, vd)) -#define VADDWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001011110, vk, vj, vd)) -#define VADDWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001011111, vk, vj, vd)) -#define VADDWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001100100, vk, vj, vd)) -#define VADDWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001100101, vk, vj, vd)) -#define VADDWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001100110, vk, vj, vd)) -#define VADDWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001100111, vk, vj, vd)) -#define VSUBWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001100000, vk, vj, vd)) -#define VSUBWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001100001, vk, vj, vd)) -#define VSUBWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001100010, vk, vj, vd)) -#define VSUBWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001100011, vk, vj, vd)) -#define VSUBWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001101000, vk, vj, vd)) -#define VSUBWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001101001, vk, vj, vd)) -#define VSUBWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001101010, vk, vj, vd)) -#define VSUBWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001101011, vk, vj, vd)) -#define VADDWEV_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000001111100, vk, vj, vd)) -#define VADDWEV_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000001111101, vk, vj, vd)) -#define VADDWEV_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000001111110, vk, vj, vd)) -#define VADDWEV_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000001111111, vk, vj, vd)) -#define VADDWOD_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000010000000, vk, vj, vd)) -#define VADDWOD_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000010000001, vk, vj, vd)) -#define VADDWOD_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000010000010, vk, vj, vd)) -#define VADDWOD_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000010000011, vk, vj, vd)) -#define VAVG_B(vd, vj, vk) EMIT(type_3R(0b01110000011001000, vk, vj, vd)) -#define VAVG_H(vd, vj, vk) EMIT(type_3R(0b01110000011001001, vk, vj, vd)) -#define VAVG_W(vd, vj, vk) EMIT(type_3R(0b01110000011001010, vk, vj, vd)) -#define VAVG_D(vd, vj, vk) EMIT(type_3R(0b01110000011001011, vk, vj, vd)) -#define VAVG_BU(vd, vj, vk) EMIT(type_3R(0b01110000011001100, vk, vj, vd)) -#define VAVG_HU(vd, vj, vk) EMIT(type_3R(0b01110000011001101, vk, vj, vd)) -#define VAVG_WU(vd, vj, vk) EMIT(type_3R(0b01110000011001110, vk, vj, vd)) -#define VAVG_DU(vd, vj, vk) EMIT(type_3R(0b01110000011001111, vk, vj, vd)) -#define VAVGR_B(vd, vj, vk) EMIT(type_3R(0b01110000011010000, vk, vj, vd)) -#define VAVGR_H(vd, vj, vk) EMIT(type_3R(0b01110000011010001, vk, vj, vd)) -#define VAVGR_W(vd, vj, vk) EMIT(type_3R(0b01110000011010010, vk, vj, vd)) -#define VAVGR_D(vd, vj, vk) EMIT(type_3R(0b01110000011010011, vk, vj, vd)) -#define VAVGR_BU(vd, vj, vk) EMIT(type_3R(0b01110000011010100, vk, vj, vd)) -#define VAVGR_HU(vd, vj, vk) EMIT(type_3R(0b01110000011010101, vk, vj, vd)) -#define VAVGR_WU(vd, vj, vk) EMIT(type_3R(0b01110000011010110, vk, vj, vd)) -#define VAVGR_DU(vd, vj, vk) EMIT(type_3R(0b01110000011010111, vk, vj, vd)) -#define VABSD_B(vd, vj, vk) EMIT(type_3R(0b01110000011000000, vk, vj, vd)) -#define VABSD_H(vd, vj, vk) EMIT(type_3R(0b01110000011000001, vk, vj, vd)) -#define VABSD_W(vd, vj, vk) EMIT(type_3R(0b01110000011000010, vk, vj, vd)) -#define VABSD_D(vd, vj, vk) EMIT(type_3R(0b01110000011000011, vk, vj, vd)) -#define VABSD_BU(vd, vj, vk) EMIT(type_3R(0b01110000011000100, vk, vj, vd)) -#define VABSD_HU(vd, vj, vk) EMIT(type_3R(0b01110000011000101, vk, vj, vd)) -#define VABSD_WU(vd, vj, vk) EMIT(type_3R(0b01110000011000110, vk, vj, vd)) -#define VABSD_DU(vd, vj, vk) EMIT(type_3R(0b01110000011000111, vk, vj, vd)) -#define VADDA_B(vd, vj, vk) EMIT(type_3R(0b01110000010111000, vk, vj, vd)) -#define VADDA_H(vd, vj, vk) EMIT(type_3R(0b01110000010111001, vk, vj, vd)) -#define VADDA_W(vd, vj, vk) EMIT(type_3R(0b01110000010111010, vk, vj, vd)) -#define VADDA_D(vd, vj, vk) EMIT(type_3R(0b01110000010111011, vk, vj, vd)) -#define VMAXI_B(vd, vj, imm5) EMIT(type_3R(0b01110010100100000, imm5, vj, vd)) -#define VMAXI_H(vd, vj, imm5) EMIT(type_3R(0b01110010100100001, imm5, vj, vd)) -#define VMAXI_W(vd, vj, imm5) EMIT(type_3R(0b01110010100100010, imm5, vj, vd)) -#define VMAXI_D(vd, vj, imm5) EMIT(type_3R(0b01110010100100011, imm5, vj, vd)) -#define VMAXI_BU(vd, vj, imm5) EMIT(type_3R(0b01110010100101000, imm5, vj, vd)) -#define VMAXI_HU(vd, vj, imm5) EMIT(type_3R(0b01110010100101001, imm5, vj, vd)) -#define VMAXI_WU(vd, vj, imm5) EMIT(type_3R(0b01110010100101010, imm5, vj, vd)) -#define VMAXI_DU(vd, vj, imm5) EMIT(type_3R(0b01110010100101011, imm5, vj, vd)) -#define VMAX_B(vd, vj, vk) EMIT(type_3R(0b01110000011100000, vk, vj, vd)) -#define VMAX_H(vd, vj, vk) EMIT(type_3R(0b01110000011100001, vk, vj, vd)) -#define VMAX_W(vd, vj, vk) EMIT(type_3R(0b01110000011100010, vk, vj, vd)) -#define VMAX_D(vd, vj, vk) EMIT(type_3R(0b01110000011100011, vk, vj, vd)) -#define VMAX_BU(vd, vj, vk) EMIT(type_3R(0b01110000011101000, vk, vj, vd)) -#define VMAX_HU(vd, vj, vk) EMIT(type_3R(0b01110000011101001, vk, vj, vd)) -#define VMAX_WU(vd, vj, vk) EMIT(type_3R(0b01110000011101010, vk, vj, vd)) -#define VMAX_DU(vd, vj, vk) EMIT(type_3R(0b01110000011101011, vk, vj, vd)) -#define VMINI_B(vd, vj, imm5) EMIT(type_3R(0b01110010100100100, imm5, vj, vd)) -#define VMINI_H(vd, vj, imm5) EMIT(type_3R(0b01110010100100101, imm5, vj, vd)) -#define VMINI_W(vd, vj, imm5) EMIT(type_3R(0b01110010100100110, imm5, vj, vd)) -#define VMINI_D(vd, vj, imm5) EMIT(type_3R(0b01110010100100111, imm5, vj, vd)) -#define VMINI_BU(vd, vj, imm5) EMIT(type_3R(0b01110010100101100, imm5, vj, vd)) -#define VMINI_HU(vd, vj, imm5) EMIT(type_3R(0b01110010100101101, imm5, vj, vd)) -#define VMINI_WU(vd, vj, imm5) EMIT(type_3R(0b01110010100101110, imm5, vj, vd)) -#define VMINI_DU(vd, vj, imm5) EMIT(type_3R(0b01110010100101111, imm5, vj, vd)) -#define VMIN_B(vd, vj, vk) EMIT(type_3R(0b01110000011100100, vk, vj, vd)) -#define VMIN_H(vd, vj, vk) EMIT(type_3R(0b01110000011100101, vk, vj, vd)) -#define VMIN_W(vd, vj, vk) EMIT(type_3R(0b01110000011100110, vk, vj, vd)) -#define VMIN_D(vd, vj, vk) EMIT(type_3R(0b01110000011100111, vk, vj, vd)) -#define VMIN_BU(vd, vj, vk) EMIT(type_3R(0b01110000011101100, vk, vj, vd)) -#define VMIN_HU(vd, vj, vk) EMIT(type_3R(0b01110000011101101, vk, vj, vd)) -#define VMIN_WU(vd, vj, vk) EMIT(type_3R(0b01110000011101110, vk, vj, vd)) -#define VMIN_DU(vd, vj, vk) EMIT(type_3R(0b01110000011101111, vk, vj, vd)) -#define VMUL_B(vd, vj, vk) EMIT(type_3R(0b01110000100001000, vk, vj, vd)) -#define VMUL_H(vd, vj, vk) EMIT(type_3R(0b01110000100001001, vk, vj, vd)) -#define VMUL_W(vd, vj, vk) EMIT(type_3R(0b01110000100001010, vk, vj, vd)) -#define VMUL_D(vd, vj, vk) EMIT(type_3R(0b01110000100001011, vk, vj, vd)) -#define VMUH_B(vd, vj, vk) EMIT(type_3R(0b01110000100001100, vk, vj, vd)) -#define VMUH_H(vd, vj, vk) EMIT(type_3R(0b01110000100001101, vk, vj, vd)) -#define VMUH_W(vd, vj, vk) EMIT(type_3R(0b01110000100001110, vk, vj, vd)) -#define VMUH_D(vd, vj, vk) EMIT(type_3R(0b01110000100001111, vk, vj, vd)) -#define VMUH_BU(vd, vj, vk) EMIT(type_3R(0b01110000100010000, vk, vj, vd)) -#define VMUH_HU(vd, vj, vk) EMIT(type_3R(0b01110000100010001, vk, vj, vd)) -#define VMUH_WU(vd, vj, vk) EMIT(type_3R(0b01110000100010010, vk, vj, vd)) -#define VMUH_DU(vd, vj, vk) EMIT(type_3R(0b01110000100010011, vk, vj, vd)) -#define VMULWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000100100000, vk, vj, vd)) -#define VMULWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000100100001, vk, vj, vd)) -#define VMULWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000100100010, vk, vj, vd)) -#define VMULWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000100100011, vk, vj, vd)) -#define VMULWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000100100100, vk, vj, vd)) -#define VMULWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000100100101, vk, vj, vd)) -#define VMULWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000100100110, vk, vj, vd)) -#define VMULWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000100100111, vk, vj, vd)) -#define VMULWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000100110000, vk, vj, vd)) -#define VMULWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000100110001, vk, vj, vd)) -#define VMULWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000100110010, vk, vj, vd)) -#define VMULWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000100110011, vk, vj, vd)) -#define VMULWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000100110100, vk, vj, vd)) -#define VMULWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000100110101, vk, vj, vd)) -#define VMULWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000100110110, vk, vj, vd)) -#define VMULWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000100110111, vk, vj, vd)) -#define VMULWEV_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101000000, vk, vj, vd)) -#define VMULWEV_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101000001, vk, vj, vd)) -#define VMULWEV_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101000010, vk, vj, vd)) -#define VMULWEV_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101000011, vk, vj, vd)) -#define VMULWOD_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101000100, vk, vj, vd)) -#define VMULWOD_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101000101, vk, vj, vd)) -#define VMULWOD_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101000110, vk, vj, vd)) -#define VMULWOD_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101000111, vk, vj, vd)) -#define VMADD_B(vd, vj, vk) EMIT(type_3R(0b01110000101010000, vk, vj, vd)) -#define VMADD_H(vd, vj, vk) EMIT(type_3R(0b01110000101010001, vk, vj, vd)) -#define VMADD_W(vd, vj, vk) EMIT(type_3R(0b01110000101010010, vk, vj, vd)) -#define VMADD_D(vd, vj, vk) EMIT(type_3R(0b01110000101010011, vk, vj, vd)) -#define VMSUB_B(vd, vj, vk) EMIT(type_3R(0b01110000101010100, vk, vj, vd)) -#define VMSUB_H(vd, vj, vk) EMIT(type_3R(0b01110000101010101, vk, vj, vd)) -#define VMSUB_W(vd, vj, vk) EMIT(type_3R(0b01110000101010110, vk, vj, vd)) -#define VMSUB_D(vd, vj, vk) EMIT(type_3R(0b01110000101010111, vk, vj, vd)) -#define VMADDWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000101011000, vk, vj, vd)) -#define VMADDWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000101011001, vk, vj, vd)) -#define VMADDWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000101011010, vk, vj, vd)) -#define VMADDWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000101011011, vk, vj, vd)) -#define VMADDWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000101011100, vk, vj, vd)) -#define VMADDWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000101011101, vk, vj, vd)) -#define VMADDWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000101011110, vk, vj, vd)) -#define VMADDWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000101011111, vk, vj, vd)) -#define VMADDWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000101101000, vk, vj, vd)) -#define VMADDWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000101101001, vk, vj, vd)) -#define VMADDWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000101101010, vk, vj, vd)) -#define VMADDWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000101101011, vk, vj, vd)) -#define VMADDWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000101101100, vk, vj, vd)) -#define VMADDWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000101101101, vk, vj, vd)) -#define VMADDWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000101101110, vk, vj, vd)) -#define VMADDWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000101101111, vk, vj, vd)) -#define VMADDWEV_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101111000, vk, vj, vd)) -#define VMADDWEV_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101111001, vk, vj, vd)) -#define VMADDWEV_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101111010, vk, vj, vd)) -#define VMADDWEV_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101111011, vk, vj, vd)) -#define VMADDWOD_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101111100, vk, vj, vd)) -#define VMADDWOD_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101111101, vk, vj, vd)) -#define VMADDWOD_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101111110, vk, vj, vd)) -#define VMADDWOD_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101111111, vk, vj, vd)) -#define VDIV_B(vd, vj, vk) EMIT(type_3R(0b01110000111000000, vk, vj, vd)) -#define VDIV_H(vd, vj, vk) EMIT(type_3R(0b01110000111000001, vk, vj, vd)) -#define VDIV_W(vd, vj, vk) EMIT(type_3R(0b01110000111000010, vk, vj, vd)) -#define VDIV_D(vd, vj, vk) EMIT(type_3R(0b01110000111000011, vk, vj, vd)) -#define VDIV_BU(vd, vj, vk) EMIT(type_3R(0b01110000111001000, vk, vj, vd)) -#define VDIV_HU(vd, vj, vk) EMIT(type_3R(0b01110000111001001, vk, vj, vd)) -#define VDIV_WU(vd, vj, vk) EMIT(type_3R(0b01110000111001010, vk, vj, vd)) -#define VDIV_DU(vd, vj, vk) EMIT(type_3R(0b01110000111001011, vk, vj, vd)) -#define VMOD_B(vd, vj, vk) EMIT(type_3R(0b01110000111000100, vk, vj, vd)) -#define VMOD_H(vd, vj, vk) EMIT(type_3R(0b01110000111000101, vk, vj, vd)) -#define VMOD_W(vd, vj, vk) EMIT(type_3R(0b01110000111000110, vk, vj, vd)) -#define VMOD_D(vd, vj, vk) EMIT(type_3R(0b01110000111000111, vk, vj, vd)) -#define VMOD_BU(vd, vj, vk) EMIT(type_3R(0b01110000111001100, vk, vj, vd)) -#define VMOD_HU(vd, vj, vk) EMIT(type_3R(0b01110000111001101, vk, vj, vd)) -#define VMOD_WU(vd, vj, vk) EMIT(type_3R(0b01110000111001110, vk, vj, vd)) -#define VMOD_DU(vd, vj, vk) EMIT(type_3R(0b01110000111001111, vk, vj, vd)) -#define VSIGNCOV_B(vd, vj, vk) EMIT(type_3R(0b01110001001011100, vk, vj, vd)) -#define VSIGNCOV_H(vd, vj, vk) EMIT(type_3R(0b01110001001011101, vk, vj, vd)) -#define VSIGNCOV_W(vd, vj, vk) EMIT(type_3R(0b01110001001011110, vk, vj, vd)) -#define VSIGNCOV_D(vd, vj, vk) EMIT(type_3R(0b01110001001011111, vk, vj, vd)) -#define VMSKLTZ_B(vd, vj) EMIT(type_2R(0b0111001010011100010000, vj, vd)) -#define VMSKLTZ_H(vd, vj) EMIT(type_2R(0b0111001010011100010001, vj, vd)) -#define VMSKLTZ_W(vd, vj) EMIT(type_2R(0b0111001010011100010010, vj, vd)) -#define VMSKLTZ_D(vd, vj) EMIT(type_2R(0b0111001010011100010011, vj, vd)) -#define VMSKGEZ_B(vd, vj) EMIT(type_2R(0b0111001010011100010100, vj, vd)) -#define VMSKNZ_B(vd, vj) EMIT(type_2R(0b0111001010011100011000, vj, vd)) -#define VAND_V(vd, vj, vk) EMIT(type_3R(0b01110001001001100, vk, vj, vd)) -#define VLDI(vd, imm13) EMIT(type_1RI13(0b01110011111000, imm13, vd)) -#define VOR_V(vd, vj, vk) EMIT(type_3R(0b01110001001001101, vk, vj, vd)) -#define VXOR_V(vd, vj, vk) EMIT(type_3R(0b01110001001001110, vk, vj, vd)) -#define VNOR_V(vd, vj, vk) EMIT(type_3R(0b01110001001001111, vk, vj, vd)) -#define VANDN_V(vd, vj, vk) EMIT(type_3R(0b01110001001010000, vk, vj, vd)) -#define VORN_V(vd, vj, vk) EMIT(type_3R(0b01110001001010001, vk, vj, vd)) -#define VSLL_B(vd, vj, vk) EMIT(type_3R(0b01110000111010000, vk, vj, vd)) -#define VSLL_H(vd, vj, vk) EMIT(type_3R(0b01110000111010001, vk, vj, vd)) -#define VSLL_W(vd, vj, vk) EMIT(type_3R(0b01110000111010010, vk, vj, vd)) -#define VSLL_D(vd, vj, vk) EMIT(type_3R(0b01110000111010011, vk, vj, vd)) -#define VSRL_B(vd, vj, vk) EMIT(type_3R(0b01110000111010100, vk, vj, vd)) -#define VSRL_H(vd, vj, vk) EMIT(type_3R(0b01110000111010101, vk, vj, vd)) -#define VSRL_W(vd, vj, vk) EMIT(type_3R(0b01110000111010110, vk, vj, vd)) -#define VSRL_D(vd, vj, vk) EMIT(type_3R(0b01110000111010111, vk, vj, vd)) -#define VSRA_B(vd, vj, vk) EMIT(type_3R(0b01110000111011000, vk, vj, vd)) -#define VSRA_H(vd, vj, vk) EMIT(type_3R(0b01110000111011001, vk, vj, vd)) -#define VSRA_W(vd, vj, vk) EMIT(type_3R(0b01110000111011010, vk, vj, vd)) -#define VSRA_D(vd, vj, vk) EMIT(type_3R(0b01110000111011011, vk, vj, vd)) -#define VSLLI_B(vd, vj, imm3) EMIT(type_2RI3(0b0111001100101100001, imm3, vj, vd)) -#define VSLLI_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110010110001, imm4, vj, vd)) -#define VSLLI_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011001011001, imm5, vj, vd)) -#define VSLLI_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001100101101, imm6, vj, vd)) -#define VSRLI_B(vd, vj, imm3) EMIT(type_2RI3(0b0111001100110000001, imm3, vj, vd)) -#define VSRLI_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110011000001, imm4, vj, vd)) -#define VSRLI_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011001100001, imm5, vj, vd)) -#define VSRLI_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001100110001, imm6, vj, vd)) -#define VSRAI_B(vd, vj, imm3) EMIT(type_2RI3(0b0111001100110100001, imm3, vj, vd)) -#define VSRAI_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110011010001, imm4, vj, vd)) -#define VSRAI_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011001101001, imm5, vj, vd)) -#define VSRAI_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001100110101, imm6, vj, vd)) -#define VROTR_B(vd, vj, vk) EMIT(type_3R(0b01110000111011100, vk, vj, vd)) -#define VROTR_H(vd, vj, vk) EMIT(type_3R(0b01110000111011101, vk, vj, vd)) -#define VROTR_W(vd, vj, vk) EMIT(type_3R(0b01110000111011110, vk, vj, vd)) -#define VROTR_D(vd, vj, vk) EMIT(type_3R(0b01110000111011111, vk, vj, vd)) -#define VSRLR_B(vd, vj, vk) EMIT(type_3R(0b01110000111100000, vk, vj, vd)) -#define VSRLR_H(vd, vj, vk) EMIT(type_3R(0b01110000111100001, vk, vj, vd)) -#define VSRLR_W(vd, vj, vk) EMIT(type_3R(0b01110000111100010, vk, vj, vd)) -#define VSRLR_D(vd, vj, vk) EMIT(type_3R(0b01110000111100011, vk, vj, vd)) -#define VSRAR_B(vd, vj, vk) EMIT(type_3R(0b01110000111100100, vk, vj, vd)) -#define VSRAR_H(vd, vj, vk) EMIT(type_3R(0b01110000111100101, vk, vj, vd)) -#define VSRAR_W(vd, vj, vk) EMIT(type_3R(0b01110000111100110, vk, vj, vd)) -#define VSRAR_D(vd, vj, vk) EMIT(type_3R(0b01110000111100111, vk, vj, vd)) -#define VSRLN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111101001, vk, vj, vd)) -#define VSRLN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111101010, vk, vj, vd)) -#define VSRLN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111101011, vk, vj, vd)) -#define VSRAN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111101101, vk, vj, vd)) -#define VSRAN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111101110, vk, vj, vd)) -#define VSRAN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111101111, vk, vj, vd)) -#define VSRLNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110100000001, imm4, vj, vd)) -#define VSRLNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010000001, imm5, vj, vd)) -#define VSRLNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101000001, imm6, vj, vd)) -#define VSRLNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110100001, imm7, vj, vd)) -#define VSRANI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110101100001, imm4, vj, vd)) -#define VSRANI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010110001, imm5, vj, vd)) -#define VSRANI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101011001, imm6, vj, vd)) -#define VSRANI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110101101, imm7, vj, vd)) -#define VSRLRN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111110001, vk, vj, vd)) -#define VSRLRN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111110010, vk, vj, vd)) -#define VSRLRN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111110011, vk, vj, vd)) -#define VSRARN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111110101, vk, vj, vd)) -#define VSRARN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111110110, vk, vj, vd)) -#define VSRARN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111110111, vk, vj, vd)) -#define VSSRLN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111111001, vk, vj, vd)) -#define VSSRLN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111111010, vk, vj, vd)) -#define VSSRLN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111111011, vk, vj, vd)) -#define VSSRAN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111111101, vk, vj, vd)) -#define VSSRAN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111111110, vk, vj, vd)) -#define VSSRAN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111111111, vk, vj, vd)) -#define VSSRLN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000001001, vk, vj, vd)) -#define VSSRLN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000001010, vk, vj, vd)) -#define VSSRLN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000001011, vk, vj, vd)) -#define VSSRAN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000001101, vk, vj, vd)) -#define VSSRAN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000001110, vk, vj, vd)) -#define VSSRAN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000001111, vk, vj, vd)) -#define VSSRLNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110100100001, imm4, vj, vd)) -#define VSSRLNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010010001, imm5, vj, vd)) -#define VSSRLNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101001001, imm6, vj, vd)) -#define VSSRLNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110100101, imm7, vj, vd)) -#define VSSRANI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110000001, imm4, vj, vd)) -#define VSSRANI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011000001, imm5, vj, vd)) -#define VSSRANI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101100001, imm6, vj, vd)) -#define VSSRANI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110001, imm7, vj, vd)) -#define VSSRLNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110100110001, imm4, vj, vd)) -#define VSSRLNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010011001, imm5, vj, vd)) -#define VSSRLNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101001101, imm6, vj, vd)) -#define VSSRLNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110100111, imm7, vj, vd)) -#define VSSRANI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110010001, imm4, vj, vd)) -#define VSSRANI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011001001, imm5, vj, vd)) -#define VSSRANI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101100101, imm6, vj, vd)) -#define VSSRANI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110011, imm7, vj, vd)) -#define VSSRLRN_B_H(vd, vj, vk) EMIT(type_3R(0b01110001000000001, vk, vj, vd)) -#define VSSRLRN_H_W(vd, vj, vk) EMIT(type_3R(0b01110001000000010, vk, vj, vd)) -#define VSSRLRN_W_D(vd, vj, vk) EMIT(type_3R(0b01110001000000011, vk, vj, vd)) -#define VSSRARN_B_H(vd, vj, vk) EMIT(type_3R(0b01110001000000101, vk, vj, vd)) -#define VSSRARN_H_W(vd, vj, vk) EMIT(type_3R(0b01110001000000110, vk, vj, vd)) -#define VSSRARN_W_D(vd, vj, vk) EMIT(type_3R(0b01110001000000111, vk, vj, vd)) -#define VSSRLRN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000010001, vk, vj, vd)) -#define VSSRLRN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000010010, vk, vj, vd)) -#define VSSRLRN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000010011, vk, vj, vd)) -#define VSSRARN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000010101, vk, vj, vd)) -#define VSSRARN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000010110, vk, vj, vd)) -#define VSSRARN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000010111, vk, vj, vd)) -#define VSSRLRNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110101000001, imm4, vj, vd)) -#define VSSRLRNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010100001, imm5, vj, vd)) -#define VSSRLRNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101010001, imm6, vj, vd)) -#define VSSRLRNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110101001, imm7, vj, vd)) -#define VSSRARNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110100001, imm4, vj, vd)) -#define VSSRARNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011010001, imm5, vj, vd)) -#define VSSRARNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101101001, imm6, vj, vd)) -#define VSSRARNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110101, imm7, vj, vd)) -#define VSSRLRNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110101010001, imm4, vj, vd)) -#define VSSRLRNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010101001, imm5, vj, vd)) -#define VSSRLRNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101010101, imm6, vj, vd)) -#define VSSRLRNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110101011, imm7, vj, vd)) -#define VSSRARNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110110001, imm4, vj, vd)) -#define VSSRARNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011011001, imm5, vj, vd)) -#define VSSRARNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101101101, imm6, vj, vd)) -#define VSSRARNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110111, imm7, vj, vd)) -#define VBITCLR_B(vd, vj, vk) EMIT(type_3R(0b01110001000011000, vk, vj, vd)) -#define VBITCLR_H(vd, vj, vk) EMIT(type_3R(0b01110001000011001, vk, vj, vd)) -#define VBITCLR_W(vd, vj, vk) EMIT(type_3R(0b01110001000011010, vk, vj, vd)) -#define VBITCLR_D(vd, vj, vk) EMIT(type_3R(0b01110001000011011, vk, vj, vd)) -#define VBITSET_B(vd, vj, vk) EMIT(type_3R(0b01110001000011100, vk, vj, vd)) -#define VBITSET_H(vd, vj, vk) EMIT(type_3R(0b01110001000011101, vk, vj, vd)) -#define VBITSET_W(vd, vj, vk) EMIT(type_3R(0b01110001000011110, vk, vj, vd)) -#define VBITSET_D(vd, vj, vk) EMIT(type_3R(0b01110001000011111, vk, vj, vd)) -#define VBITREV_B(vd, vj, vk) EMIT(type_3R(0b01110001000100000, vk, vj, vd)) -#define VBITREV_H(vd, vj, vk) EMIT(type_3R(0b01110001000100001, vk, vj, vd)) -#define VBITREV_W(vd, vj, vk) EMIT(type_3R(0b01110001000100010, vk, vj, vd)) -#define VBITREV_D(vd, vj, vk) EMIT(type_3R(0b01110001000100011, vk, vj, vd)) -#define VFRSTP_B(vd, vj, vk) EMIT(type_3R(0b01110001001010110, vk, vj, vd)) -#define VFRSTP_H(vd, vj, vk) EMIT(type_3R(0b01110001001010111, vk, vj, vd)) -#define VFADD_S(vd, vj, vk) EMIT(type_3R(0b01110001001100001, vk, vj, vd)) -#define VFADD_D(vd, vj, vk) EMIT(type_3R(0b01110001001100010, vk, vj, vd)) -#define VFSUB_S(vd, vj, vk) EMIT(type_3R(0b01110001001100101, vk, vj, vd)) -#define VFSUB_D(vd, vj, vk) EMIT(type_3R(0b01110001001100110, vk, vj, vd)) -#define VFMUL_S(vd, vj, vk) EMIT(type_3R(0b01110001001110001, vk, vj, vd)) -#define VFMUL_D(vd, vj, vk) EMIT(type_3R(0b01110001001110010, vk, vj, vd)) -#define VFDIV_S(vd, vj, vk) EMIT(type_3R(0b01110001001110101, vk, vj, vd)) -#define VFDIV_D(vd, vj, vk) EMIT(type_3R(0b01110001001110110, vk, vj, vd)) -#define VFMAX_S(vd, vj, vk) EMIT(type_3R(0b01110001001111001, vk, vj, vd)) -#define VFMAX_D(vd, vj, vk) EMIT(type_3R(0b01110001001111010, vk, vj, vd)) -#define VFMIN_S(vd, vj, vk) EMIT(type_3R(0b01110001001111101, vk, vj, vd)) -#define VFMIN_D(vd, vj, vk) EMIT(type_3R(0b01110001001111110, vk, vj, vd)) -#define VFMAXA_S(vd, vj, vk) EMIT(type_3R(0b01110001010000001, vk, vj, vd)) -#define VFMAXA_D(vd, vj, vk) EMIT(type_3R(0b01110001010000010, vk, vj, vd)) -#define VFMINA_S(vd, vj, vk) EMIT(type_3R(0b01110001010000101, vk, vj, vd)) -#define VFMINA_D(vd, vj, vk) EMIT(type_3R(0b01110001010000110, vk, vj, vd)) -#define VFSQRT_S(vd, vj) EMIT(type_2R(0b0111001010011100111001, vj, vd)) -#define VFSQRT_D(vd, vj) EMIT(type_2R(0b0111001010011100111010, vj, vd)) -#define VFRECIP_S(vd, vj) EMIT(type_2R(0b0111001010011100111101, vj, vd)) -#define VFRECIP_D(vd, vj) EMIT(type_2R(0b0111001010011100111110, vj, vd)) -#define VFRSQRT_S(vd, vj) EMIT(type_2R(0b0111001010011101000001, vj, vd)) -#define VFRSQRT_D(vd, vj) EMIT(type_2R(0b0111001010011101000010, vj, vd)) -#define VFCVTL_S_H(vd, vj) EMIT(type_2R(0b0111001010011101111010, vj, vd)) -#define VFCVTH_S_H(vd, vj) EMIT(type_2R(0b0111001010011101111011, vj, vd)) -#define VFCVTL_D_S(vd, vj) EMIT(type_2R(0b0111001010011101111100, vj, vd)) -#define VFCVTH_D_S(vd, vj) EMIT(type_2R(0b0111001010011101111101, vj, vd)) -#define VFCVT_H_S(vd, vj, vk) EMIT(type_3R(0b01110001010001100, vk, vj, vd)) -#define VFCVT_S_D(vd, vj, vk) EMIT(type_3R(0b01110001010001101, vk, vj, vd)) -#define VFTINT_W_S(vd, vj) EMIT(type_2R(0b0111001010011110001100, vj, vd)) -#define VFTINT_L_D(vd, vj) EMIT(type_2R(0b0111001010011110001101, vj, vd)) -#define VFTINTRM_W_S(vd, vj) EMIT(type_2R(0b0111001010011110001110, vj, vd)) -#define VFTINTRM_L_D(vd, vj) EMIT(type_2R(0b0111001010011110001111, vj, vd)) -#define VFTINTRP_W_S(vd, vj) EMIT(type_2R(0b0111001010011110010000, vj, vd)) -#define VFTINTRP_L_D(vd, vj) EMIT(type_2R(0b0111001010011110010001, vj, vd)) -#define VFTINTRZ_W_S(vd, vj) EMIT(type_2R(0b0111001010011110010010, vj, vd)) -#define VFTINTRZ_L_D(vd, vj) EMIT(type_2R(0b0111001010011110010011, vj, vd)) -#define VFTINTRNE_W_S(vd, vj) EMIT(type_2R(0b0111001010011110010100, vj, vd)) -#define VFTINTRNE_L_D(vd, vj) EMIT(type_2R(0b0111001010011110010101, vj, vd)) -#define VFTINT_WU_S(vd, vj) EMIT(type_2R(0b0111001010011110010110, vj, vd)) -#define VFTINT_LU_D(vd, vj) EMIT(type_2R(0b0111001010011110010111, vj, vd)) -#define VFTINTRZ_WU_S(vd, vj) EMIT(type_2R(0b0111001010011110011100, vj, vd)) -#define VFTINTRZ_LU_D(vd, vj) EMIT(type_2R(0b0111001010011110011101, vj, vd)) -#define VFTINT_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010011, vk, vj, vd)) -#define VFTINTRM_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010100, vk, vj, vd)) -#define VFTINTRP_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010101, vk, vj, vd)) -#define VFTINTRZ_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010110, vk, vj, vd)) -#define VFTINTRNE_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010111, vk, vj, vd)) -#define VFTINTL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100000, vj, vd)) -#define VFTINTH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100001, vj, vd)) -#define VFTINTRML_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100010, vj, vd)) -#define VFTINTRMH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100011, vj, vd)) -#define VFTINTRPL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100100, vj, vd)) -#define VFTINTRPH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100101, vj, vd)) -#define VFTINTRZL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100110, vj, vd)) -#define VFTINTRZH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100111, vj, vd)) -#define VFTINTRNEL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110101000, vj, vd)) -#define VFTINTRNEH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110101001, vj, vd)) -#define VFFINT_S_W(vd, vj) EMIT(type_2R(0b0111001010011110000000, vj, vd)) -#define VFFINT_S_WU(vd, vj) EMIT(type_2R(0b0111001010011110000001, vj, vd)) -#define VFFINT_D_L(vd, vj) EMIT(type_2R(0b0111001010011110000010, vj, vd)) -#define VFFINT_D_LU(vd, vj) EMIT(type_2R(0b0111001010011110000011, vj, vd)) -#define VFFINTL_D_W(vd, vj) EMIT(type_2R(0b0111001010011110000100, vj, vd)) -#define VFFINTH_D_W(vd, vj) EMIT(type_2R(0b0111001010011110000101, vj, vd)) -#define VFFINT_S_L(vd, vj, vk) EMIT(type_3R(0b01110001010010000, vk, vj, vd)) -#define VSEQ_B(vd, vj, vk) EMIT(type_3R(0b01110000000000000, vk, vj, vd)) -#define VSEQ_H(vd, vj, vk) EMIT(type_3R(0b01110000000000001, vk, vj, vd)) -#define VSEQ_W(vd, vj, vk) EMIT(type_3R(0b01110000000000010, vk, vj, vd)) -#define VSEQ_D(vd, vj, vk) EMIT(type_3R(0b01110000000000011, vk, vj, vd)) -#define VSLE_B(vd, vj, vk) EMIT(type_3R(0b01110000000000100, vk, vj, vd)) -#define VSLE_H(vd, vj, vk) EMIT(type_3R(0b01110000000000101, vk, vj, vd)) -#define VSLE_W(vd, vj, vk) EMIT(type_3R(0b01110000000000110, vk, vj, vd)) -#define VSLE_D(vd, vj, vk) EMIT(type_3R(0b01110000000000111, vk, vj, vd)) -#define VSLE_BU(vd, vj, vk) EMIT(type_3R(0b01110000000001000, vk, vj, vd)) -#define VSLE_HU(vd, vj, vk) EMIT(type_3R(0b01110000000001001, vk, vj, vd)) -#define VSLE_WU(vd, vj, vk) EMIT(type_3R(0b01110000000001010, vk, vj, vd)) -#define VSLE_DU(vd, vj, vk) EMIT(type_3R(0b01110000000001011, vk, vj, vd)) -#define VSLT_B(vd, vj, vk) EMIT(type_3R(0b01110000000001100, vk, vj, vd)) -#define VSLT_H(vd, vj, vk) EMIT(type_3R(0b01110000000001101, vk, vj, vd)) -#define VSLT_W(vd, vj, vk) EMIT(type_3R(0b01110000000001110, vk, vj, vd)) -#define VSLT_D(vd, vj, vk) EMIT(type_3R(0b01110000000001111, vk, vj, vd)) -#define VSLT_BU(vd, vj, vk) EMIT(type_3R(0b01110000000010000, vk, vj, vd)) -#define VSLT_HU(vd, vj, vk) EMIT(type_3R(0b01110000000010001, vk, vj, vd)) -#define VSLT_WU(vd, vj, vk) EMIT(type_3R(0b01110000000010010, vk, vj, vd)) -#define VSLT_DU(vd, vj, vk) EMIT(type_3R(0b01110000000010011, vk, vj, vd)) -#define VREPLVE_B(vd, vj, rk) EMIT(type_3R(0b01110001001000100, rk, vj, vd)) -#define VREPLVE_H(vd, vj, rk) EMIT(type_3R(0b01110001001000101, rk, vj, vd)) -#define VREPLVE_W(vd, vj, rk) EMIT(type_3R(0b01110001001000110, rk, vj, vd)) -#define VREPLVE_D(vd, vj, rk) EMIT(type_3R(0b01110001001000111, rk, vj, vd)) -#define VREPLVEI_B(vd, vk, imm4) EMIT(type_2RI4(0b011100101111011110, imm4, vk, vd)) -#define VREPLVEI_H(vd, vk, imm3) EMIT(type_2RI3(0b0111001011110111110, imm3, vk, vd)) -#define VREPLVEI_W(vd, vk, imm2) EMIT(type_2RI2(0b01110010111101111110, imm2, vk, vd)) -#define VREPLVEI_D(vd, vk, imm1) EMIT(type_2RI1(0b011100101111011111110, imm1, vk, vd)) -#define VBSLL_V(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011100, imm5, vj, vd)) -#define VBSRL_V(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011101, imm5, vj, vd)) -#define VPACKEV_B(vd, vj, vk) EMIT(type_3R(0b01110001000101100, vk, vj, vd)) -#define VPACKEV_H(vd, vj, vk) EMIT(type_3R(0b01110001000101101, vk, vj, vd)) -#define VPACKEV_W(vd, vj, vk) EMIT(type_3R(0b01110001000101110, vk, vj, vd)) -#define VPACKEV_D(vd, vj, vk) EMIT(type_3R(0b01110001000101111, vk, vj, vd)) -#define VPACKOD_B(vd, vj, vk) EMIT(type_3R(0b01110001000110000, vk, vj, vd)) -#define VPACKOD_H(vd, vj, vk) EMIT(type_3R(0b01110001000110001, vk, vj, vd)) -#define VPACKOD_W(vd, vj, vk) EMIT(type_3R(0b01110001000110010, vk, vj, vd)) -#define VPACKOD_D(vd, vj, vk) EMIT(type_3R(0b01110001000110011, vk, vj, vd)) -#define VPICKEV_B(vd, vj, vk) EMIT(type_3R(0b01110001000111100, vk, vj, vd)) -#define VPICKEV_H(vd, vj, vk) EMIT(type_3R(0b01110001000111101, vk, vj, vd)) -#define VPICKEV_W(vd, vj, vk) EMIT(type_3R(0b01110001000111110, vk, vj, vd)) -#define VPICKEV_D(vd, vj, vk) EMIT(type_3R(0b01110001000111111, vk, vj, vd)) -#define VPICKOD_B(vd, vj, vk) EMIT(type_3R(0b01110001001000000, vk, vj, vd)) -#define VPICKOD_H(vd, vj, vk) EMIT(type_3R(0b01110001001000001, vk, vj, vd)) -#define VPICKOD_W(vd, vj, vk) EMIT(type_3R(0b01110001001000010, vk, vj, vd)) -#define VPICKOD_D(vd, vj, vk) EMIT(type_3R(0b01110001001000011, vk, vj, vd)) -#define VILVL_B(vd, vj, vk) EMIT(type_3R(0b01110001000110100, vk, vj, vd)) -#define VILVL_H(vd, vj, vk) EMIT(type_3R(0b01110001000110101, vk, vj, vd)) -#define VILVL_W(vd, vj, vk) EMIT(type_3R(0b01110001000110110, vk, vj, vd)) -#define VILVL_D(vd, vj, vk) EMIT(type_3R(0b01110001000110111, vk, vj, vd)) -#define VILVH_B(vd, vj, vk) EMIT(type_3R(0b01110001000111000, vk, vj, vd)) -#define VILVH_H(vd, vj, vk) EMIT(type_3R(0b01110001000111001, vk, vj, vd)) -#define VILVH_W(vd, vj, vk) EMIT(type_3R(0b01110001000111010, vk, vj, vd)) -#define VILVH_D(vd, vj, vk) EMIT(type_3R(0b01110001000111011, vk, vj, vd)) -#define VSHUF_B(vd, vj, vk, va) EMIT(type_4R(0b000011010101, va, vk, vj, vd)) -#define VSHUF_H(vd, vj, vk) EMIT(type_3R(0b01110001011110101, vk, vj, vd)) -#define VSHUF_W(vd, vj, vk) EMIT(type_3R(0b01110001011110110, vk, vj, vd)) -#define VSHUF_D(vd, vj, vk) EMIT(type_3R(0b01110001011110111, vk, vj, vd)) -#define VSHUF4I_B(vd, vj, imm8) EMIT(type_2RI8(0b01110011100100, imm8, vj, vd)) -#define VSHUF4I_H(vd, vj, imm8) EMIT(type_2RI8(0b01110011100101, imm8, vj, vd)) -#define VSHUF4I_W(vd, vj, imm8) EMIT(type_2RI8(0b01110011100110, imm8, vj, vd)) -#define VSHUF4I_D(vd, vj, imm8) EMIT(type_2RI8(0b01110011100111, imm8, vj, vd)) -#define VEXTRINS_D(vd, vj, imm8) EMIT(type_2RI8(0b01110011100000, imm8, vj, vd)) -#define VEXTRINS_W(vd, vj, imm8) EMIT(type_2RI8(0b01110011100001, imm8, vj, vd)) -#define VEXTRINS_H(vd, vj, imm8) EMIT(type_2RI8(0b01110011100010, imm8, vj, vd)) -#define VEXTRINS_B(vd, vj, imm8) EMIT(type_2RI8(0b01110011100011, imm8, vj, vd)) -#define VLD(vd, rj, imm12) EMIT(type_2RI12(0b0010110000, imm12, rj, vd)) -#define VST(vd, rj, imm12) EMIT(type_2RI12(0b0010110001, imm12, rj, vd)) - -#define VFCMP_S(vd, vj, vk, cond) EMIT(type_4R(0b000011000101, cond, vk, vj, vd)) -#define VFCMP_D(vd, vj, vk, cond) EMIT(type_4R(0b000011000110, cond, vk, vj, vd)) - +#define VADD_B(vd, vj, vk) EMIT(type_3R(0b01110000000010100, vk, vj, vd)) +#define VADD_H(vd, vj, vk) EMIT(type_3R(0b01110000000010101, vk, vj, vd)) +#define VADD_W(vd, vj, vk) EMIT(type_3R(0b01110000000010110, vk, vj, vd)) +#define VADD_D(vd, vj, vk) EMIT(type_3R(0b01110000000010111, vk, vj, vd)) +#define VADD_Q(vd, vj, vk) EMIT(type_3R(0b01110001001011010, vk, vj, vd)) +#define VSUB_B(vd, vj, vk) EMIT(type_3R(0b01110000000011000, vk, vj, vd)) +#define VSUB_H(vd, vj, vk) EMIT(type_3R(0b01110000000011001, vk, vj, vd)) +#define VSUB_W(vd, vj, vk) EMIT(type_3R(0b01110000000011010, vk, vj, vd)) +#define VSUB_D(vd, vj, vk) EMIT(type_3R(0b01110000000011011, vk, vj, vd)) +#define VSUB_Q(vd, vj, vk) EMIT(type_3R(0b01110001001011011, vk, vj, vd)) +#define VADDI_BU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010100, imm5, vj, vd)) +#define VADDI_HU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010101, imm5, vj, vd)) +#define VADDI_WU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010110, imm5, vj, vd)) +#define VADDI_DU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100010111, imm5, vj, vd)) +#define VSUBI_BU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011000, imm5, vj, vd)) +#define VSUBI_HU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011001, imm5, vj, vd)) +#define VSUBI_WU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011010, imm5, vj, vd)) +#define VSUBI_DU(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011011, imm5, vj, vd)) +#define VSADD_B(vd, vj, vk) EMIT(type_3R(0b01110000010001100, vk, vj, vd)) +#define VSADD_H(vd, vj, vk) EMIT(type_3R(0b01110000010001101, vk, vj, vd)) +#define VSADD_W(vd, vj, vk) EMIT(type_3R(0b01110000010001110, vk, vj, vd)) +#define VSADD_D(vd, vj, vk) EMIT(type_3R(0b01110000010001111, vk, vj, vd)) +#define VSADD_BU(vd, vj, vk) EMIT(type_3R(0b01110000010010100, vk, vj, vd)) +#define VSADD_HU(vd, vj, vk) EMIT(type_3R(0b01110000010010101, vk, vj, vd)) +#define VSADD_WU(vd, vj, vk) EMIT(type_3R(0b01110000010010110, vk, vj, vd)) +#define VSADD_DU(vd, vj, vk) EMIT(type_3R(0b01110000010010111, vk, vj, vd)) +#define VSSUB_B(vd, vj, vk) EMIT(type_3R(0b01110000010010000, vk, vj, vd)) +#define VSSUB_H(vd, vj, vk) EMIT(type_3R(0b01110000010010001, vk, vj, vd)) +#define VSSUB_W(vd, vj, vk) EMIT(type_3R(0b01110000010010010, vk, vj, vd)) +#define VSSUB_D(vd, vj, vk) EMIT(type_3R(0b01110000010010011, vk, vj, vd)) +#define VSSUB_BU(vd, vj, vk) EMIT(type_3R(0b01110000010011000, vk, vj, vd)) +#define VSSUB_HU(vd, vj, vk) EMIT(type_3R(0b01110000010011001, vk, vj, vd)) +#define VSSUB_WU(vd, vj, vk) EMIT(type_3R(0b01110000010011010, vk, vj, vd)) +#define VSSUB_DU(vd, vj, vk) EMIT(type_3R(0b01110000010011011, vk, vj, vd)) +#define VHADDW_H_B(vd, vj, vk) EMIT(type_3R(0b01110000010101000, vk, vj, vd)) +#define VHADDW_W_H(vd, vj, vk) EMIT(type_3R(0b01110000010101001, vk, vj, vd)) +#define VHADDW_D_W(vd, vj, vk) EMIT(type_3R(0b01110000010101010, vk, vj, vd)) +#define VHADDW_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000010101011, vk, vj, vd)) +#define VHADDW_HU_BU(vd, vj, vk) EMIT(type_3R(0b01110000010110000, vk, vj, vd)) +#define VHADDW_WU_HU(vd, vj, vk) EMIT(type_3R(0b01110000010110001, vk, vj, vd)) +#define VHADDW_DU_WU(vd, vj, vk) EMIT(type_3R(0b01110000010110010, vk, vj, vd)) +#define VHADDW_QU_DU(vd, vj, vk) EMIT(type_3R(0b01110000010110011, vk, vj, vd)) +#define VHSUBW_H_B(vd, vj, vk) EMIT(type_3R(0b01110000010101100, vk, vj, vd)) +#define VHSUBW_W_H(vd, vj, vk) EMIT(type_3R(0b01110000010101101, vk, vj, vd)) +#define VHSUBW_D_W(vd, vj, vk) EMIT(type_3R(0b01110000010101110, vk, vj, vd)) +#define VHSUBW_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000010101111, vk, vj, vd)) +#define VHSUBW_HU_BU(vd, vj, vk) EMIT(type_3R(0b01110000010110100, vk, vj, vd)) +#define VHSUBW_WU_HU(vd, vj, vk) EMIT(type_3R(0b01110000010110101, vk, vj, vd)) +#define VHSUBW_DU_WU(vd, vj, vk) EMIT(type_3R(0b01110000010110110, vk, vj, vd)) +#define VHSUBW_QU_DU(vd, vj, vk) EMIT(type_3R(0b01110000010110111, vk, vj, vd)) +#define VADDWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000000111100, vk, vj, vd)) +#define VADDWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000000111101, vk, vj, vd)) +#define VADDWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000000111110, vk, vj, vd)) +#define VADDWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000000111111, vk, vj, vd)) +#define VADDWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000001000100, vk, vj, vd)) +#define VADDWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000001000101, vk, vj, vd)) +#define VADDWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000001000110, vk, vj, vd)) +#define VADDWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000001000111, vk, vj, vd)) +#define VSUBWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000001000000, vk, vj, vd)) +#define VSUBWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000001000001, vk, vj, vd)) +#define VSUBWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000001000010, vk, vj, vd)) +#define VSUBWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000001000011, vk, vj, vd)) +#define VSUBWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000001001000, vk, vj, vd)) +#define VSUBWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000001001001, vk, vj, vd)) +#define VSUBWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000001001010, vk, vj, vd)) +#define VSUBWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000001001011, vk, vj, vd)) +#define VADDWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001011100, vk, vj, vd)) +#define VADDWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001011101, vk, vj, vd)) +#define VADDWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001011110, vk, vj, vd)) +#define VADDWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001011111, vk, vj, vd)) +#define VADDWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001100100, vk, vj, vd)) +#define VADDWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001100101, vk, vj, vd)) +#define VADDWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001100110, vk, vj, vd)) +#define VADDWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001100111, vk, vj, vd)) +#define VSUBWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001100000, vk, vj, vd)) +#define VSUBWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001100001, vk, vj, vd)) +#define VSUBWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001100010, vk, vj, vd)) +#define VSUBWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001100011, vk, vj, vd)) +#define VSUBWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000001101000, vk, vj, vd)) +#define VSUBWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000001101001, vk, vj, vd)) +#define VSUBWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000001101010, vk, vj, vd)) +#define VSUBWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000001101011, vk, vj, vd)) +#define VADDWEV_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000001111100, vk, vj, vd)) +#define VADDWEV_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000001111101, vk, vj, vd)) +#define VADDWEV_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000001111110, vk, vj, vd)) +#define VADDWEV_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000001111111, vk, vj, vd)) +#define VADDWOD_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000010000000, vk, vj, vd)) +#define VADDWOD_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000010000001, vk, vj, vd)) +#define VADDWOD_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000010000010, vk, vj, vd)) +#define VADDWOD_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000010000011, vk, vj, vd)) +#define VAVG_B(vd, vj, vk) EMIT(type_3R(0b01110000011001000, vk, vj, vd)) +#define VAVG_H(vd, vj, vk) EMIT(type_3R(0b01110000011001001, vk, vj, vd)) +#define VAVG_W(vd, vj, vk) EMIT(type_3R(0b01110000011001010, vk, vj, vd)) +#define VAVG_D(vd, vj, vk) EMIT(type_3R(0b01110000011001011, vk, vj, vd)) +#define VAVG_BU(vd, vj, vk) EMIT(type_3R(0b01110000011001100, vk, vj, vd)) +#define VAVG_HU(vd, vj, vk) EMIT(type_3R(0b01110000011001101, vk, vj, vd)) +#define VAVG_WU(vd, vj, vk) EMIT(type_3R(0b01110000011001110, vk, vj, vd)) +#define VAVG_DU(vd, vj, vk) EMIT(type_3R(0b01110000011001111, vk, vj, vd)) +#define VAVGR_B(vd, vj, vk) EMIT(type_3R(0b01110000011010000, vk, vj, vd)) +#define VAVGR_H(vd, vj, vk) EMIT(type_3R(0b01110000011010001, vk, vj, vd)) +#define VAVGR_W(vd, vj, vk) EMIT(type_3R(0b01110000011010010, vk, vj, vd)) +#define VAVGR_D(vd, vj, vk) EMIT(type_3R(0b01110000011010011, vk, vj, vd)) +#define VAVGR_BU(vd, vj, vk) EMIT(type_3R(0b01110000011010100, vk, vj, vd)) +#define VAVGR_HU(vd, vj, vk) EMIT(type_3R(0b01110000011010101, vk, vj, vd)) +#define VAVGR_WU(vd, vj, vk) EMIT(type_3R(0b01110000011010110, vk, vj, vd)) +#define VAVGR_DU(vd, vj, vk) EMIT(type_3R(0b01110000011010111, vk, vj, vd)) +#define VABSD_B(vd, vj, vk) EMIT(type_3R(0b01110000011000000, vk, vj, vd)) +#define VABSD_H(vd, vj, vk) EMIT(type_3R(0b01110000011000001, vk, vj, vd)) +#define VABSD_W(vd, vj, vk) EMIT(type_3R(0b01110000011000010, vk, vj, vd)) +#define VABSD_D(vd, vj, vk) EMIT(type_3R(0b01110000011000011, vk, vj, vd)) +#define VABSD_BU(vd, vj, vk) EMIT(type_3R(0b01110000011000100, vk, vj, vd)) +#define VABSD_HU(vd, vj, vk) EMIT(type_3R(0b01110000011000101, vk, vj, vd)) +#define VABSD_WU(vd, vj, vk) EMIT(type_3R(0b01110000011000110, vk, vj, vd)) +#define VABSD_DU(vd, vj, vk) EMIT(type_3R(0b01110000011000111, vk, vj, vd)) +#define VADDA_B(vd, vj, vk) EMIT(type_3R(0b01110000010111000, vk, vj, vd)) +#define VADDA_H(vd, vj, vk) EMIT(type_3R(0b01110000010111001, vk, vj, vd)) +#define VADDA_W(vd, vj, vk) EMIT(type_3R(0b01110000010111010, vk, vj, vd)) +#define VADDA_D(vd, vj, vk) EMIT(type_3R(0b01110000010111011, vk, vj, vd)) +#define VMAXI_B(vd, vj, imm5) EMIT(type_3R(0b01110010100100000, imm5, vj, vd)) +#define VMAXI_H(vd, vj, imm5) EMIT(type_3R(0b01110010100100001, imm5, vj, vd)) +#define VMAXI_W(vd, vj, imm5) EMIT(type_3R(0b01110010100100010, imm5, vj, vd)) +#define VMAXI_D(vd, vj, imm5) EMIT(type_3R(0b01110010100100011, imm5, vj, vd)) +#define VMAXI_BU(vd, vj, imm5) EMIT(type_3R(0b01110010100101000, imm5, vj, vd)) +#define VMAXI_HU(vd, vj, imm5) EMIT(type_3R(0b01110010100101001, imm5, vj, vd)) +#define VMAXI_WU(vd, vj, imm5) EMIT(type_3R(0b01110010100101010, imm5, vj, vd)) +#define VMAXI_DU(vd, vj, imm5) EMIT(type_3R(0b01110010100101011, imm5, vj, vd)) +#define VMAX_B(vd, vj, vk) EMIT(type_3R(0b01110000011100000, vk, vj, vd)) +#define VMAX_H(vd, vj, vk) EMIT(type_3R(0b01110000011100001, vk, vj, vd)) +#define VMAX_W(vd, vj, vk) EMIT(type_3R(0b01110000011100010, vk, vj, vd)) +#define VMAX_D(vd, vj, vk) EMIT(type_3R(0b01110000011100011, vk, vj, vd)) +#define VMAX_BU(vd, vj, vk) EMIT(type_3R(0b01110000011101000, vk, vj, vd)) +#define VMAX_HU(vd, vj, vk) EMIT(type_3R(0b01110000011101001, vk, vj, vd)) +#define VMAX_WU(vd, vj, vk) EMIT(type_3R(0b01110000011101010, vk, vj, vd)) +#define VMAX_DU(vd, vj, vk) EMIT(type_3R(0b01110000011101011, vk, vj, vd)) +#define VMINI_B(vd, vj, imm5) EMIT(type_3R(0b01110010100100100, imm5, vj, vd)) +#define VMINI_H(vd, vj, imm5) EMIT(type_3R(0b01110010100100101, imm5, vj, vd)) +#define VMINI_W(vd, vj, imm5) EMIT(type_3R(0b01110010100100110, imm5, vj, vd)) +#define VMINI_D(vd, vj, imm5) EMIT(type_3R(0b01110010100100111, imm5, vj, vd)) +#define VMINI_BU(vd, vj, imm5) EMIT(type_3R(0b01110010100101100, imm5, vj, vd)) +#define VMINI_HU(vd, vj, imm5) EMIT(type_3R(0b01110010100101101, imm5, vj, vd)) +#define VMINI_WU(vd, vj, imm5) EMIT(type_3R(0b01110010100101110, imm5, vj, vd)) +#define VMINI_DU(vd, vj, imm5) EMIT(type_3R(0b01110010100101111, imm5, vj, vd)) +#define VMIN_B(vd, vj, vk) EMIT(type_3R(0b01110000011100100, vk, vj, vd)) +#define VMIN_H(vd, vj, vk) EMIT(type_3R(0b01110000011100101, vk, vj, vd)) +#define VMIN_W(vd, vj, vk) EMIT(type_3R(0b01110000011100110, vk, vj, vd)) +#define VMIN_D(vd, vj, vk) EMIT(type_3R(0b01110000011100111, vk, vj, vd)) +#define VMIN_BU(vd, vj, vk) EMIT(type_3R(0b01110000011101100, vk, vj, vd)) +#define VMIN_HU(vd, vj, vk) EMIT(type_3R(0b01110000011101101, vk, vj, vd)) +#define VMIN_WU(vd, vj, vk) EMIT(type_3R(0b01110000011101110, vk, vj, vd)) +#define VMIN_DU(vd, vj, vk) EMIT(type_3R(0b01110000011101111, vk, vj, vd)) +#define VMUL_B(vd, vj, vk) EMIT(type_3R(0b01110000100001000, vk, vj, vd)) +#define VMUL_H(vd, vj, vk) EMIT(type_3R(0b01110000100001001, vk, vj, vd)) +#define VMUL_W(vd, vj, vk) EMIT(type_3R(0b01110000100001010, vk, vj, vd)) +#define VMUL_D(vd, vj, vk) EMIT(type_3R(0b01110000100001011, vk, vj, vd)) +#define VMUH_B(vd, vj, vk) EMIT(type_3R(0b01110000100001100, vk, vj, vd)) +#define VMUH_H(vd, vj, vk) EMIT(type_3R(0b01110000100001101, vk, vj, vd)) +#define VMUH_W(vd, vj, vk) EMIT(type_3R(0b01110000100001110, vk, vj, vd)) +#define VMUH_D(vd, vj, vk) EMIT(type_3R(0b01110000100001111, vk, vj, vd)) +#define VMUH_BU(vd, vj, vk) EMIT(type_3R(0b01110000100010000, vk, vj, vd)) +#define VMUH_HU(vd, vj, vk) EMIT(type_3R(0b01110000100010001, vk, vj, vd)) +#define VMUH_WU(vd, vj, vk) EMIT(type_3R(0b01110000100010010, vk, vj, vd)) +#define VMUH_DU(vd, vj, vk) EMIT(type_3R(0b01110000100010011, vk, vj, vd)) +#define VMULWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000100100000, vk, vj, vd)) +#define VMULWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000100100001, vk, vj, vd)) +#define VMULWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000100100010, vk, vj, vd)) +#define VMULWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000100100011, vk, vj, vd)) +#define VMULWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000100100100, vk, vj, vd)) +#define VMULWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000100100101, vk, vj, vd)) +#define VMULWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000100100110, vk, vj, vd)) +#define VMULWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000100100111, vk, vj, vd)) +#define VMULWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000100110000, vk, vj, vd)) +#define VMULWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000100110001, vk, vj, vd)) +#define VMULWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000100110010, vk, vj, vd)) +#define VMULWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000100110011, vk, vj, vd)) +#define VMULWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000100110100, vk, vj, vd)) +#define VMULWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000100110101, vk, vj, vd)) +#define VMULWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000100110110, vk, vj, vd)) +#define VMULWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000100110111, vk, vj, vd)) +#define VMULWEV_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101000000, vk, vj, vd)) +#define VMULWEV_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101000001, vk, vj, vd)) +#define VMULWEV_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101000010, vk, vj, vd)) +#define VMULWEV_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101000011, vk, vj, vd)) +#define VMULWOD_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101000100, vk, vj, vd)) +#define VMULWOD_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101000101, vk, vj, vd)) +#define VMULWOD_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101000110, vk, vj, vd)) +#define VMULWOD_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101000111, vk, vj, vd)) +#define VMADD_B(vd, vj, vk) EMIT(type_3R(0b01110000101010000, vk, vj, vd)) +#define VMADD_H(vd, vj, vk) EMIT(type_3R(0b01110000101010001, vk, vj, vd)) +#define VMADD_W(vd, vj, vk) EMIT(type_3R(0b01110000101010010, vk, vj, vd)) +#define VMADD_D(vd, vj, vk) EMIT(type_3R(0b01110000101010011, vk, vj, vd)) +#define VMSUB_B(vd, vj, vk) EMIT(type_3R(0b01110000101010100, vk, vj, vd)) +#define VMSUB_H(vd, vj, vk) EMIT(type_3R(0b01110000101010101, vk, vj, vd)) +#define VMSUB_W(vd, vj, vk) EMIT(type_3R(0b01110000101010110, vk, vj, vd)) +#define VMSUB_D(vd, vj, vk) EMIT(type_3R(0b01110000101010111, vk, vj, vd)) +#define VMADDWEV_H_B(vd, vj, vk) EMIT(type_3R(0b01110000101011000, vk, vj, vd)) +#define VMADDWEV_W_H(vd, vj, vk) EMIT(type_3R(0b01110000101011001, vk, vj, vd)) +#define VMADDWEV_D_W(vd, vj, vk) EMIT(type_3R(0b01110000101011010, vk, vj, vd)) +#define VMADDWEV_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000101011011, vk, vj, vd)) +#define VMADDWOD_H_B(vd, vj, vk) EMIT(type_3R(0b01110000101011100, vk, vj, vd)) +#define VMADDWOD_W_H(vd, vj, vk) EMIT(type_3R(0b01110000101011101, vk, vj, vd)) +#define VMADDWOD_D_W(vd, vj, vk) EMIT(type_3R(0b01110000101011110, vk, vj, vd)) +#define VMADDWOD_Q_D(vd, vj, vk) EMIT(type_3R(0b01110000101011111, vk, vj, vd)) +#define VMADDWEV_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000101101000, vk, vj, vd)) +#define VMADDWEV_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000101101001, vk, vj, vd)) +#define VMADDWEV_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000101101010, vk, vj, vd)) +#define VMADDWEV_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000101101011, vk, vj, vd)) +#define VMADDWOD_H_BU(vd, vj, vk) EMIT(type_3R(0b01110000101101100, vk, vj, vd)) +#define VMADDWOD_W_HU(vd, vj, vk) EMIT(type_3R(0b01110000101101101, vk, vj, vd)) +#define VMADDWOD_D_WU(vd, vj, vk) EMIT(type_3R(0b01110000101101110, vk, vj, vd)) +#define VMADDWOD_Q_DU(vd, vj, vk) EMIT(type_3R(0b01110000101101111, vk, vj, vd)) +#define VMADDWEV_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101111000, vk, vj, vd)) +#define VMADDWEV_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101111001, vk, vj, vd)) +#define VMADDWEV_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101111010, vk, vj, vd)) +#define VMADDWEV_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101111011, vk, vj, vd)) +#define VMADDWOD_H_BU_B(vd, vj, vk) EMIT(type_3R(0b01110000101111100, vk, vj, vd)) +#define VMADDWOD_W_HU_H(vd, vj, vk) EMIT(type_3R(0b01110000101111101, vk, vj, vd)) +#define VMADDWOD_D_WU_W(vd, vj, vk) EMIT(type_3R(0b01110000101111110, vk, vj, vd)) +#define VMADDWOD_Q_DU_D(vd, vj, vk) EMIT(type_3R(0b01110000101111111, vk, vj, vd)) +#define VDIV_B(vd, vj, vk) EMIT(type_3R(0b01110000111000000, vk, vj, vd)) +#define VDIV_H(vd, vj, vk) EMIT(type_3R(0b01110000111000001, vk, vj, vd)) +#define VDIV_W(vd, vj, vk) EMIT(type_3R(0b01110000111000010, vk, vj, vd)) +#define VDIV_D(vd, vj, vk) EMIT(type_3R(0b01110000111000011, vk, vj, vd)) +#define VDIV_BU(vd, vj, vk) EMIT(type_3R(0b01110000111001000, vk, vj, vd)) +#define VDIV_HU(vd, vj, vk) EMIT(type_3R(0b01110000111001001, vk, vj, vd)) +#define VDIV_WU(vd, vj, vk) EMIT(type_3R(0b01110000111001010, vk, vj, vd)) +#define VDIV_DU(vd, vj, vk) EMIT(type_3R(0b01110000111001011, vk, vj, vd)) +#define VMOD_B(vd, vj, vk) EMIT(type_3R(0b01110000111000100, vk, vj, vd)) +#define VMOD_H(vd, vj, vk) EMIT(type_3R(0b01110000111000101, vk, vj, vd)) +#define VMOD_W(vd, vj, vk) EMIT(type_3R(0b01110000111000110, vk, vj, vd)) +#define VMOD_D(vd, vj, vk) EMIT(type_3R(0b01110000111000111, vk, vj, vd)) +#define VMOD_BU(vd, vj, vk) EMIT(type_3R(0b01110000111001100, vk, vj, vd)) +#define VMOD_HU(vd, vj, vk) EMIT(type_3R(0b01110000111001101, vk, vj, vd)) +#define VMOD_WU(vd, vj, vk) EMIT(type_3R(0b01110000111001110, vk, vj, vd)) +#define VMOD_DU(vd, vj, vk) EMIT(type_3R(0b01110000111001111, vk, vj, vd)) +#define VSIGNCOV_B(vd, vj, vk) EMIT(type_3R(0b01110001001011100, vk, vj, vd)) +#define VSIGNCOV_H(vd, vj, vk) EMIT(type_3R(0b01110001001011101, vk, vj, vd)) +#define VSIGNCOV_W(vd, vj, vk) EMIT(type_3R(0b01110001001011110, vk, vj, vd)) +#define VSIGNCOV_D(vd, vj, vk) EMIT(type_3R(0b01110001001011111, vk, vj, vd)) +#define VMSKLTZ_B(vd, vj) EMIT(type_2R(0b0111001010011100010000, vj, vd)) +#define VMSKLTZ_H(vd, vj) EMIT(type_2R(0b0111001010011100010001, vj, vd)) +#define VMSKLTZ_W(vd, vj) EMIT(type_2R(0b0111001010011100010010, vj, vd)) +#define VMSKLTZ_D(vd, vj) EMIT(type_2R(0b0111001010011100010011, vj, vd)) +#define VMSKGEZ_B(vd, vj) EMIT(type_2R(0b0111001010011100010100, vj, vd)) +#define VMSKNZ_B(vd, vj) EMIT(type_2R(0b0111001010011100011000, vj, vd)) +#define VAND_V(vd, vj, vk) EMIT(type_3R(0b01110001001001100, vk, vj, vd)) +#define VLDI(vd, imm13) EMIT(type_1RI13(0b01110011111000, imm13, vd)) +#define VOR_V(vd, vj, vk) EMIT(type_3R(0b01110001001001101, vk, vj, vd)) +#define VXOR_V(vd, vj, vk) EMIT(type_3R(0b01110001001001110, vk, vj, vd)) +#define VNOR_V(vd, vj, vk) EMIT(type_3R(0b01110001001001111, vk, vj, vd)) +#define VANDN_V(vd, vj, vk) EMIT(type_3R(0b01110001001010000, vk, vj, vd)) +#define VORN_V(vd, vj, vk) EMIT(type_3R(0b01110001001010001, vk, vj, vd)) +#define VSLL_B(vd, vj, vk) EMIT(type_3R(0b01110000111010000, vk, vj, vd)) +#define VSLL_H(vd, vj, vk) EMIT(type_3R(0b01110000111010001, vk, vj, vd)) +#define VSLL_W(vd, vj, vk) EMIT(type_3R(0b01110000111010010, vk, vj, vd)) +#define VSLL_D(vd, vj, vk) EMIT(type_3R(0b01110000111010011, vk, vj, vd)) +#define VSRL_B(vd, vj, vk) EMIT(type_3R(0b01110000111010100, vk, vj, vd)) +#define VSRL_H(vd, vj, vk) EMIT(type_3R(0b01110000111010101, vk, vj, vd)) +#define VSRL_W(vd, vj, vk) EMIT(type_3R(0b01110000111010110, vk, vj, vd)) +#define VSRL_D(vd, vj, vk) EMIT(type_3R(0b01110000111010111, vk, vj, vd)) +#define VSRA_B(vd, vj, vk) EMIT(type_3R(0b01110000111011000, vk, vj, vd)) +#define VSRA_H(vd, vj, vk) EMIT(type_3R(0b01110000111011001, vk, vj, vd)) +#define VSRA_W(vd, vj, vk) EMIT(type_3R(0b01110000111011010, vk, vj, vd)) +#define VSRA_D(vd, vj, vk) EMIT(type_3R(0b01110000111011011, vk, vj, vd)) +#define VSLLI_B(vd, vj, imm3) EMIT(type_2RI3(0b0111001100101100001, imm3, vj, vd)) +#define VSLLI_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110010110001, imm4, vj, vd)) +#define VSLLI_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011001011001, imm5, vj, vd)) +#define VSLLI_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001100101101, imm6, vj, vd)) +#define VSRLI_B(vd, vj, imm3) EMIT(type_2RI3(0b0111001100110000001, imm3, vj, vd)) +#define VSRLI_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110011000001, imm4, vj, vd)) +#define VSRLI_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011001100001, imm5, vj, vd)) +#define VSRLI_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001100110001, imm6, vj, vd)) +#define VSRAI_B(vd, vj, imm3) EMIT(type_2RI3(0b0111001100110100001, imm3, vj, vd)) +#define VSRAI_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110011010001, imm4, vj, vd)) +#define VSRAI_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011001101001, imm5, vj, vd)) +#define VSRAI_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001100110101, imm6, vj, vd)) +#define VROTR_B(vd, vj, vk) EMIT(type_3R(0b01110000111011100, vk, vj, vd)) +#define VROTR_H(vd, vj, vk) EMIT(type_3R(0b01110000111011101, vk, vj, vd)) +#define VROTR_W(vd, vj, vk) EMIT(type_3R(0b01110000111011110, vk, vj, vd)) +#define VROTR_D(vd, vj, vk) EMIT(type_3R(0b01110000111011111, vk, vj, vd)) +#define VSRLR_B(vd, vj, vk) EMIT(type_3R(0b01110000111100000, vk, vj, vd)) +#define VSRLR_H(vd, vj, vk) EMIT(type_3R(0b01110000111100001, vk, vj, vd)) +#define VSRLR_W(vd, vj, vk) EMIT(type_3R(0b01110000111100010, vk, vj, vd)) +#define VSRLR_D(vd, vj, vk) EMIT(type_3R(0b01110000111100011, vk, vj, vd)) +#define VSRAR_B(vd, vj, vk) EMIT(type_3R(0b01110000111100100, vk, vj, vd)) +#define VSRAR_H(vd, vj, vk) EMIT(type_3R(0b01110000111100101, vk, vj, vd)) +#define VSRAR_W(vd, vj, vk) EMIT(type_3R(0b01110000111100110, vk, vj, vd)) +#define VSRAR_D(vd, vj, vk) EMIT(type_3R(0b01110000111100111, vk, vj, vd)) +#define VSRLN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111101001, vk, vj, vd)) +#define VSRLN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111101010, vk, vj, vd)) +#define VSRLN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111101011, vk, vj, vd)) +#define VSRAN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111101101, vk, vj, vd)) +#define VSRAN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111101110, vk, vj, vd)) +#define VSRAN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111101111, vk, vj, vd)) +#define VSRLNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110100000001, imm4, vj, vd)) +#define VSRLNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010000001, imm5, vj, vd)) +#define VSRLNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101000001, imm6, vj, vd)) +#define VSRLNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110100001, imm7, vj, vd)) +#define VSRANI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110101100001, imm4, vj, vd)) +#define VSRANI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010110001, imm5, vj, vd)) +#define VSRANI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101011001, imm6, vj, vd)) +#define VSRANI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110101101, imm7, vj, vd)) +#define VSRLRN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111110001, vk, vj, vd)) +#define VSRLRN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111110010, vk, vj, vd)) +#define VSRLRN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111110011, vk, vj, vd)) +#define VSRARN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111110101, vk, vj, vd)) +#define VSRARN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111110110, vk, vj, vd)) +#define VSRARN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111110111, vk, vj, vd)) +#define VSSRLN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111111001, vk, vj, vd)) +#define VSSRLN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111111010, vk, vj, vd)) +#define VSSRLN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111111011, vk, vj, vd)) +#define VSSRAN_B_H(vd, vj, vk) EMIT(type_3R(0b01110000111111101, vk, vj, vd)) +#define VSSRAN_H_W(vd, vj, vk) EMIT(type_3R(0b01110000111111110, vk, vj, vd)) +#define VSSRAN_W_D(vd, vj, vk) EMIT(type_3R(0b01110000111111111, vk, vj, vd)) +#define VSSRLN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000001001, vk, vj, vd)) +#define VSSRLN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000001010, vk, vj, vd)) +#define VSSRLN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000001011, vk, vj, vd)) +#define VSSRAN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000001101, vk, vj, vd)) +#define VSSRAN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000001110, vk, vj, vd)) +#define VSSRAN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000001111, vk, vj, vd)) +#define VSSRLNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110100100001, imm4, vj, vd)) +#define VSSRLNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010010001, imm5, vj, vd)) +#define VSSRLNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101001001, imm6, vj, vd)) +#define VSSRLNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110100101, imm7, vj, vd)) +#define VSSRANI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110000001, imm4, vj, vd)) +#define VSSRANI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011000001, imm5, vj, vd)) +#define VSSRANI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101100001, imm6, vj, vd)) +#define VSSRANI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110001, imm7, vj, vd)) +#define VSSRLNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110100110001, imm4, vj, vd)) +#define VSSRLNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010011001, imm5, vj, vd)) +#define VSSRLNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101001101, imm6, vj, vd)) +#define VSSRLNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110100111, imm7, vj, vd)) +#define VSSRANI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110010001, imm4, vj, vd)) +#define VSSRANI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011001001, imm5, vj, vd)) +#define VSSRANI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101100101, imm6, vj, vd)) +#define VSSRANI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110011, imm7, vj, vd)) +#define VSSRLRN_B_H(vd, vj, vk) EMIT(type_3R(0b01110001000000001, vk, vj, vd)) +#define VSSRLRN_H_W(vd, vj, vk) EMIT(type_3R(0b01110001000000010, vk, vj, vd)) +#define VSSRLRN_W_D(vd, vj, vk) EMIT(type_3R(0b01110001000000011, vk, vj, vd)) +#define VSSRARN_B_H(vd, vj, vk) EMIT(type_3R(0b01110001000000101, vk, vj, vd)) +#define VSSRARN_H_W(vd, vj, vk) EMIT(type_3R(0b01110001000000110, vk, vj, vd)) +#define VSSRARN_W_D(vd, vj, vk) EMIT(type_3R(0b01110001000000111, vk, vj, vd)) +#define VSSRLRN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000010001, vk, vj, vd)) +#define VSSRLRN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000010010, vk, vj, vd)) +#define VSSRLRN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000010011, vk, vj, vd)) +#define VSSRARN_BU_H(vd, vj, vk) EMIT(type_3R(0b01110001000010101, vk, vj, vd)) +#define VSSRARN_HU_W(vd, vj, vk) EMIT(type_3R(0b01110001000010110, vk, vj, vd)) +#define VSSRARN_WU_D(vd, vj, vk) EMIT(type_3R(0b01110001000010111, vk, vj, vd)) +#define VSSRLRNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110101000001, imm4, vj, vd)) +#define VSSRLRNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010100001, imm5, vj, vd)) +#define VSSRLRNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101010001, imm6, vj, vd)) +#define VSSRLRNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110101001, imm7, vj, vd)) +#define VSSRARNI_B_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110100001, imm4, vj, vd)) +#define VSSRARNI_H_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011010001, imm5, vj, vd)) +#define VSSRARNI_W_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101101001, imm6, vj, vd)) +#define VSSRARNI_D_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110101, imm7, vj, vd)) +#define VSSRLRNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110101010001, imm4, vj, vd)) +#define VSSRLRNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011010101001, imm5, vj, vd)) +#define VSSRLRNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101010101, imm6, vj, vd)) +#define VSSRLRNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110101011, imm7, vj, vd)) +#define VSSRARNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011100110110110001, imm4, vj, vd)) +#define VSSRARNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110011011011001, imm5, vj, vd)) +#define VSSRARNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111001101101101, imm6, vj, vd)) +#define VSSRARNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011100110110111, imm7, vj, vd)) +#define VBITCLR_B(vd, vj, vk) EMIT(type_3R(0b01110001000011000, vk, vj, vd)) +#define VBITCLR_H(vd, vj, vk) EMIT(type_3R(0b01110001000011001, vk, vj, vd)) +#define VBITCLR_W(vd, vj, vk) EMIT(type_3R(0b01110001000011010, vk, vj, vd)) +#define VBITCLR_D(vd, vj, vk) EMIT(type_3R(0b01110001000011011, vk, vj, vd)) +#define VBITSET_B(vd, vj, vk) EMIT(type_3R(0b01110001000011100, vk, vj, vd)) +#define VBITSET_H(vd, vj, vk) EMIT(type_3R(0b01110001000011101, vk, vj, vd)) +#define VBITSET_W(vd, vj, vk) EMIT(type_3R(0b01110001000011110, vk, vj, vd)) +#define VBITSET_D(vd, vj, vk) EMIT(type_3R(0b01110001000011111, vk, vj, vd)) +#define VBITREV_B(vd, vj, vk) EMIT(type_3R(0b01110001000100000, vk, vj, vd)) +#define VBITREV_H(vd, vj, vk) EMIT(type_3R(0b01110001000100001, vk, vj, vd)) +#define VBITREV_W(vd, vj, vk) EMIT(type_3R(0b01110001000100010, vk, vj, vd)) +#define VBITREV_D(vd, vj, vk) EMIT(type_3R(0b01110001000100011, vk, vj, vd)) +#define VFRSTP_B(vd, vj, vk) EMIT(type_3R(0b01110001001010110, vk, vj, vd)) +#define VFRSTP_H(vd, vj, vk) EMIT(type_3R(0b01110001001010111, vk, vj, vd)) +#define VFADD_S(vd, vj, vk) EMIT(type_3R(0b01110001001100001, vk, vj, vd)) +#define VFADD_D(vd, vj, vk) EMIT(type_3R(0b01110001001100010, vk, vj, vd)) +#define VFSUB_S(vd, vj, vk) EMIT(type_3R(0b01110001001100101, vk, vj, vd)) +#define VFSUB_D(vd, vj, vk) EMIT(type_3R(0b01110001001100110, vk, vj, vd)) +#define VFMUL_S(vd, vj, vk) EMIT(type_3R(0b01110001001110001, vk, vj, vd)) +#define VFMUL_D(vd, vj, vk) EMIT(type_3R(0b01110001001110010, vk, vj, vd)) +#define VFDIV_S(vd, vj, vk) EMIT(type_3R(0b01110001001110101, vk, vj, vd)) +#define VFDIV_D(vd, vj, vk) EMIT(type_3R(0b01110001001110110, vk, vj, vd)) +#define VFMAX_S(vd, vj, vk) EMIT(type_3R(0b01110001001111001, vk, vj, vd)) +#define VFMAX_D(vd, vj, vk) EMIT(type_3R(0b01110001001111010, vk, vj, vd)) +#define VFMIN_S(vd, vj, vk) EMIT(type_3R(0b01110001001111101, vk, vj, vd)) +#define VFMIN_D(vd, vj, vk) EMIT(type_3R(0b01110001001111110, vk, vj, vd)) +#define VFMAXA_S(vd, vj, vk) EMIT(type_3R(0b01110001010000001, vk, vj, vd)) +#define VFMAXA_D(vd, vj, vk) EMIT(type_3R(0b01110001010000010, vk, vj, vd)) +#define VFMINA_S(vd, vj, vk) EMIT(type_3R(0b01110001010000101, vk, vj, vd)) +#define VFMINA_D(vd, vj, vk) EMIT(type_3R(0b01110001010000110, vk, vj, vd)) +#define VFSQRT_S(vd, vj) EMIT(type_2R(0b0111001010011100111001, vj, vd)) +#define VFSQRT_D(vd, vj) EMIT(type_2R(0b0111001010011100111010, vj, vd)) +#define VFRECIP_S(vd, vj) EMIT(type_2R(0b0111001010011100111101, vj, vd)) +#define VFRECIP_D(vd, vj) EMIT(type_2R(0b0111001010011100111110, vj, vd)) +#define VFRSQRT_S(vd, vj) EMIT(type_2R(0b0111001010011101000001, vj, vd)) +#define VFRSQRT_D(vd, vj) EMIT(type_2R(0b0111001010011101000010, vj, vd)) +#define VFCVTL_S_H(vd, vj) EMIT(type_2R(0b0111001010011101111010, vj, vd)) +#define VFCVTH_S_H(vd, vj) EMIT(type_2R(0b0111001010011101111011, vj, vd)) +#define VFCVTL_D_S(vd, vj) EMIT(type_2R(0b0111001010011101111100, vj, vd)) +#define VFCVTH_D_S(vd, vj) EMIT(type_2R(0b0111001010011101111101, vj, vd)) +#define VFCVT_H_S(vd, vj, vk) EMIT(type_3R(0b01110001010001100, vk, vj, vd)) +#define VFCVT_S_D(vd, vj, vk) EMIT(type_3R(0b01110001010001101, vk, vj, vd)) +#define VFTINT_W_S(vd, vj) EMIT(type_2R(0b0111001010011110001100, vj, vd)) +#define VFTINT_L_D(vd, vj) EMIT(type_2R(0b0111001010011110001101, vj, vd)) +#define VFTINTRM_W_S(vd, vj) EMIT(type_2R(0b0111001010011110001110, vj, vd)) +#define VFTINTRM_L_D(vd, vj) EMIT(type_2R(0b0111001010011110001111, vj, vd)) +#define VFTINTRP_W_S(vd, vj) EMIT(type_2R(0b0111001010011110010000, vj, vd)) +#define VFTINTRP_L_D(vd, vj) EMIT(type_2R(0b0111001010011110010001, vj, vd)) +#define VFTINTRZ_W_S(vd, vj) EMIT(type_2R(0b0111001010011110010010, vj, vd)) +#define VFTINTRZ_L_D(vd, vj) EMIT(type_2R(0b0111001010011110010011, vj, vd)) +#define VFTINTRNE_W_S(vd, vj) EMIT(type_2R(0b0111001010011110010100, vj, vd)) +#define VFTINTRNE_L_D(vd, vj) EMIT(type_2R(0b0111001010011110010101, vj, vd)) +#define VFTINT_WU_S(vd, vj) EMIT(type_2R(0b0111001010011110010110, vj, vd)) +#define VFTINT_LU_D(vd, vj) EMIT(type_2R(0b0111001010011110010111, vj, vd)) +#define VFTINTRZ_WU_S(vd, vj) EMIT(type_2R(0b0111001010011110011100, vj, vd)) +#define VFTINTRZ_LU_D(vd, vj) EMIT(type_2R(0b0111001010011110011101, vj, vd)) +#define VFTINT_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010011, vk, vj, vd)) +#define VFTINTRM_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010100, vk, vj, vd)) +#define VFTINTRP_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010101, vk, vj, vd)) +#define VFTINTRZ_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010110, vk, vj, vd)) +#define VFTINTRNE_W_D(vd, vj, vk) EMIT(type_3R(0b01110001010010111, vk, vj, vd)) +#define VFTINTL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100000, vj, vd)) +#define VFTINTH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100001, vj, vd)) +#define VFTINTRML_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100010, vj, vd)) +#define VFTINTRMH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100011, vj, vd)) +#define VFTINTRPL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100100, vj, vd)) +#define VFTINTRPH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100101, vj, vd)) +#define VFTINTRZL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100110, vj, vd)) +#define VFTINTRZH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110100111, vj, vd)) +#define VFTINTRNEL_L_S(vd, vj) EMIT(type_2R(0b0111001010011110101000, vj, vd)) +#define VFTINTRNEH_L_S(vd, vj) EMIT(type_2R(0b0111001010011110101001, vj, vd)) +#define VFFINT_S_W(vd, vj) EMIT(type_2R(0b0111001010011110000000, vj, vd)) +#define VFFINT_S_WU(vd, vj) EMIT(type_2R(0b0111001010011110000001, vj, vd)) +#define VFFINT_D_L(vd, vj) EMIT(type_2R(0b0111001010011110000010, vj, vd)) +#define VFFINT_D_LU(vd, vj) EMIT(type_2R(0b0111001010011110000011, vj, vd)) +#define VFFINTL_D_W(vd, vj) EMIT(type_2R(0b0111001010011110000100, vj, vd)) +#define VFFINTH_D_W(vd, vj) EMIT(type_2R(0b0111001010011110000101, vj, vd)) +#define VFFINT_S_L(vd, vj, vk) EMIT(type_3R(0b01110001010010000, vk, vj, vd)) +#define VSEQ_B(vd, vj, vk) EMIT(type_3R(0b01110000000000000, vk, vj, vd)) +#define VSEQ_H(vd, vj, vk) EMIT(type_3R(0b01110000000000001, vk, vj, vd)) +#define VSEQ_W(vd, vj, vk) EMIT(type_3R(0b01110000000000010, vk, vj, vd)) +#define VSEQ_D(vd, vj, vk) EMIT(type_3R(0b01110000000000011, vk, vj, vd)) +#define VSLE_B(vd, vj, vk) EMIT(type_3R(0b01110000000000100, vk, vj, vd)) +#define VSLE_H(vd, vj, vk) EMIT(type_3R(0b01110000000000101, vk, vj, vd)) +#define VSLE_W(vd, vj, vk) EMIT(type_3R(0b01110000000000110, vk, vj, vd)) +#define VSLE_D(vd, vj, vk) EMIT(type_3R(0b01110000000000111, vk, vj, vd)) +#define VSLE_BU(vd, vj, vk) EMIT(type_3R(0b01110000000001000, vk, vj, vd)) +#define VSLE_HU(vd, vj, vk) EMIT(type_3R(0b01110000000001001, vk, vj, vd)) +#define VSLE_WU(vd, vj, vk) EMIT(type_3R(0b01110000000001010, vk, vj, vd)) +#define VSLE_DU(vd, vj, vk) EMIT(type_3R(0b01110000000001011, vk, vj, vd)) +#define VSLT_B(vd, vj, vk) EMIT(type_3R(0b01110000000001100, vk, vj, vd)) +#define VSLT_H(vd, vj, vk) EMIT(type_3R(0b01110000000001101, vk, vj, vd)) +#define VSLT_W(vd, vj, vk) EMIT(type_3R(0b01110000000001110, vk, vj, vd)) +#define VSLT_D(vd, vj, vk) EMIT(type_3R(0b01110000000001111, vk, vj, vd)) +#define VSLT_BU(vd, vj, vk) EMIT(type_3R(0b01110000000010000, vk, vj, vd)) +#define VSLT_HU(vd, vj, vk) EMIT(type_3R(0b01110000000010001, vk, vj, vd)) +#define VSLT_WU(vd, vj, vk) EMIT(type_3R(0b01110000000010010, vk, vj, vd)) +#define VSLT_DU(vd, vj, vk) EMIT(type_3R(0b01110000000010011, vk, vj, vd)) +#define VREPLVE_B(vd, vj, rk) EMIT(type_3R(0b01110001001000100, rk, vj, vd)) +#define VREPLVE_H(vd, vj, rk) EMIT(type_3R(0b01110001001000101, rk, vj, vd)) +#define VREPLVE_W(vd, vj, rk) EMIT(type_3R(0b01110001001000110, rk, vj, vd)) +#define VREPLVE_D(vd, vj, rk) EMIT(type_3R(0b01110001001000111, rk, vj, vd)) +#define VREPLVEI_B(vd, vk, imm4) EMIT(type_2RI4(0b011100101111011110, imm4, vk, vd)) +#define VREPLVEI_H(vd, vk, imm3) EMIT(type_2RI3(0b0111001011110111110, imm3, vk, vd)) +#define VREPLVEI_W(vd, vk, imm2) EMIT(type_2RI2(0b01110010111101111110, imm2, vk, vd)) +#define VREPLVEI_D(vd, vk, imm1) EMIT(type_2RI1(0b011100101111011111110, imm1, vk, vd)) +#define VBSLL_V(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011100, imm5, vj, vd)) +#define VBSRL_V(vd, vj, imm5) EMIT(type_2RI5(0b01110010100011101, imm5, vj, vd)) +#define VPACKEV_B(vd, vj, vk) EMIT(type_3R(0b01110001000101100, vk, vj, vd)) +#define VPACKEV_H(vd, vj, vk) EMIT(type_3R(0b01110001000101101, vk, vj, vd)) +#define VPACKEV_W(vd, vj, vk) EMIT(type_3R(0b01110001000101110, vk, vj, vd)) +#define VPACKEV_D(vd, vj, vk) EMIT(type_3R(0b01110001000101111, vk, vj, vd)) +#define VPACKOD_B(vd, vj, vk) EMIT(type_3R(0b01110001000110000, vk, vj, vd)) +#define VPACKOD_H(vd, vj, vk) EMIT(type_3R(0b01110001000110001, vk, vj, vd)) +#define VPACKOD_W(vd, vj, vk) EMIT(type_3R(0b01110001000110010, vk, vj, vd)) +#define VPACKOD_D(vd, vj, vk) EMIT(type_3R(0b01110001000110011, vk, vj, vd)) +#define VPICKEV_B(vd, vj, vk) EMIT(type_3R(0b01110001000111100, vk, vj, vd)) +#define VPICKEV_H(vd, vj, vk) EMIT(type_3R(0b01110001000111101, vk, vj, vd)) +#define VPICKEV_W(vd, vj, vk) EMIT(type_3R(0b01110001000111110, vk, vj, vd)) +#define VPICKEV_D(vd, vj, vk) EMIT(type_3R(0b01110001000111111, vk, vj, vd)) +#define VPICKOD_B(vd, vj, vk) EMIT(type_3R(0b01110001001000000, vk, vj, vd)) +#define VPICKOD_H(vd, vj, vk) EMIT(type_3R(0b01110001001000001, vk, vj, vd)) +#define VPICKOD_W(vd, vj, vk) EMIT(type_3R(0b01110001001000010, vk, vj, vd)) +#define VPICKOD_D(vd, vj, vk) EMIT(type_3R(0b01110001001000011, vk, vj, vd)) +#define VILVL_B(vd, vj, vk) EMIT(type_3R(0b01110001000110100, vk, vj, vd)) +#define VILVL_H(vd, vj, vk) EMIT(type_3R(0b01110001000110101, vk, vj, vd)) +#define VILVL_W(vd, vj, vk) EMIT(type_3R(0b01110001000110110, vk, vj, vd)) +#define VILVL_D(vd, vj, vk) EMIT(type_3R(0b01110001000110111, vk, vj, vd)) +#define VILVH_B(vd, vj, vk) EMIT(type_3R(0b01110001000111000, vk, vj, vd)) +#define VILVH_H(vd, vj, vk) EMIT(type_3R(0b01110001000111001, vk, vj, vd)) +#define VILVH_W(vd, vj, vk) EMIT(type_3R(0b01110001000111010, vk, vj, vd)) +#define VILVH_D(vd, vj, vk) EMIT(type_3R(0b01110001000111011, vk, vj, vd)) +#define VSHUF_B(vd, vj, vk, va) EMIT(type_4R(0b000011010101, va, vk, vj, vd)) +#define VSHUF_H(vd, vj, vk) EMIT(type_3R(0b01110001011110101, vk, vj, vd)) +#define VSHUF_W(vd, vj, vk) EMIT(type_3R(0b01110001011110110, vk, vj, vd)) +#define VSHUF_D(vd, vj, vk) EMIT(type_3R(0b01110001011110111, vk, vj, vd)) +#define VSHUF4I_B(vd, vj, imm8) EMIT(type_2RI8(0b01110011100100, imm8, vj, vd)) +#define VSHUF4I_H(vd, vj, imm8) EMIT(type_2RI8(0b01110011100101, imm8, vj, vd)) +#define VSHUF4I_W(vd, vj, imm8) EMIT(type_2RI8(0b01110011100110, imm8, vj, vd)) +#define VSHUF4I_D(vd, vj, imm8) EMIT(type_2RI8(0b01110011100111, imm8, vj, vd)) +#define VEXTRINS_D(vd, vj, imm8) EMIT(type_2RI8(0b01110011100000, imm8, vj, vd)) +#define VEXTRINS_W(vd, vj, imm8) EMIT(type_2RI8(0b01110011100001, imm8, vj, vd)) +#define VEXTRINS_H(vd, vj, imm8) EMIT(type_2RI8(0b01110011100010, imm8, vj, vd)) +#define VEXTRINS_B(vd, vj, imm8) EMIT(type_2RI8(0b01110011100011, imm8, vj, vd)) +#define VLD(vd, rj, imm12) EMIT(type_2RI12(0b0010110000, imm12, rj, vd)) +#define VST(vd, rj, imm12) EMIT(type_2RI12(0b0010110001, imm12, rj, vd)) +#define VLDREPL_D(vd, rj, imm9) EMIT(type_2RI9(0b0011000000010, imm9, rj, vd)) +#define VLDREPL_W(vd, rj, imm10) EMIT(type_2RI10(0b001100000010, imm10, rj, vd)) +#define VLDREPL_H(vd, rj, imm11) EMIT(type_2RI11(0b00110000010, imm11, rj, vd)) +#define VLDREPL_B(vd, rj, imm12) EMIT(type_2RI12(0b0011000010, imm12, rj, vd)) +#define VFCMP_S(vd, vj, vk, cond) EMIT(type_4R(0b000011000101, cond, vk, vj, vd)) +#define VFCMP_D(vd, vj, vk, cond) EMIT(type_4R(0b000011000110, cond, vk, vj, vd)) #define XVADD_B(vd, vj, vk) EMIT(type_3R(0b01110100000010100, vk, vj, vd)) #define XVADD_H(vd, vj, vk) EMIT(type_3R(0b01110100000010101, vk, vj, vd)) #define XVADD_W(vd, vj, vk) EMIT(type_3R(0b01110100000010110, vk, vj, vd)) @@ -1809,7 +1814,6 @@ LSX instruction starts with V, LASX instruction starts with XV. #define XVPERMI_W(vd, vj, imm8) EMIT(type_2RI8(0b01110111111001, imm8, vj, vd)) #define XVPERMI_D(vd, vj, imm8) EMIT(type_2RI8(0b01110111111010, imm8, vj, vd)) #define XVPERMI_Q(vd, vj, imm8) EMIT(type_2RI8(0b01110111111011, imm8, vj, vd)) - #define VEXT2XV_H_B(vd, vj) EMIT(type_2R(0b0111011010011111000100, vj, vd)) #define VEXT2XV_W_B(vd, vj) EMIT(type_2R(0b0111011010011111000101, vj, vd)) #define VEXT2XV_D_B(vd, vj) EMIT(type_2R(0b0111011010011111000110, vj, vd)) @@ -1854,7 +1858,7 @@ LSX instruction starts with V, LASX instruction starts with XV. // GET/SET LBT4.ftop #define X64_SET_TOP(imm3) EMIT(0x00007000 | ((imm3 & 0b111) << 5)) -#define X64_GET_TOP(rd) EMIT(type_2R(0x00007400, 0, rd)) +#define X64_GET_TOP(rd) EMIT(type_2R(0x00007400, 0, rd)) #define X64_GET_EFLAGS(rd, mask8) EMIT(type_2RI8(0x17, mask8, 0, rd)) #define X64_SET_EFLAGS(rd, mask8) EMIT(type_2RI8(0x17, mask8, 1, rd)) @@ -1881,110 +1885,110 @@ LSX instruction starts with V, LASX instruction starts with XV. // Note that these instructions only affect the LBT4.eflags. -#define X64_INC_B(rj) EMIT(type_2R(0x20, rj, 0x0)) -#define X64_INC_H(rj) EMIT(type_2R(0x20, rj, 0x1)) -#define X64_INC_W(rj) EMIT(type_2R(0x20, rj, 0x2)) -#define X64_INC_D(rj) EMIT(type_2R(0x20, rj, 0x3)) -#define X64_DEC_B(rj) EMIT(type_2R(0x20, rj, 0x4)) -#define X64_DEC_H(rj) EMIT(type_2R(0x20, rj, 0x5)) -#define X64_DEC_W(rj) EMIT(type_2R(0x20, rj, 0x6)) -#define X64_DEC_D(rj) EMIT(type_2R(0x20, rj, 0x7)) -#define X64_MUL_B(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x0)) -#define X64_MUL_H(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x1)) -#define X64_MUL_W(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x2)) -#define X64_MUL_D(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x3)) -#define X64_MUL_BU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x4)) -#define X64_MUL_HU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x5)) -#define X64_MUL_WU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x6)) -#define X64_MUL_DU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x7)) -#define X64_ADD_WU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x0)) -#define X64_ADD_DU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1)) -#define X64_SUB_WU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x2)) -#define X64_SUB_DU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x3)) -#define X64_ADD_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x4)) -#define X64_ADD_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x5)) -#define X64_ADD_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x6)) -#define X64_ADD_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x7)) -#define X64_SUB_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x8)) -#define X64_SUB_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x9)) -#define X64_SUB_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xa)) -#define X64_SUB_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xb)) -#define X64_ADC_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xc)) -#define X64_ADC_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xd)) -#define X64_ADC_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xe)) -#define X64_ADC_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xf)) -#define X64_SBC_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x10)) -#define X64_SBC_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x11)) -#define X64_SBC_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x12)) -#define X64_SBC_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x13)) -#define X64_SLL_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x14)) -#define X64_SLL_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x15)) -#define X64_SLL_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x16)) -#define X64_SLL_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x17)) -#define X64_SRL_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x18)) -#define X64_SRL_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x19)) -#define X64_SRL_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1a)) -#define X64_SRL_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1b)) -#define X64_SRA_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1c)) -#define X64_SRA_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1d)) -#define X64_SRA_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1e)) -#define X64_SRA_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1f)) -#define X64_ROTR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x0)) -#define X64_ROTR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x1)) -#define X64_ROTR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x2)) -#define X64_ROTR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x3)) -#define X64_ROTL_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x4)) -#define X64_ROTL_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x5)) -#define X64_ROTL_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x6)) -#define X64_ROTL_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x7)) -#define X64_RCR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x8)) -#define X64_RCR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x9)) -#define X64_RCR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xa)) -#define X64_RCR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xb)) -#define X64_RCL_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xc)) -#define X64_RCL_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xd)) -#define X64_RCL_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xe)) -#define X64_RCL_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xf)) -#define X64_AND_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x10)) -#define X64_AND_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x11)) -#define X64_AND_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x12)) -#define X64_AND_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x13)) -#define X64_OR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x14)) -#define X64_OR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x15)) -#define X64_OR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x16)) -#define X64_OR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x17)) -#define X64_XOR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x18)) -#define X64_XOR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x19)) -#define X64_XOR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x1a)) -#define X64_XOR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x1b)) -#define X64_SLLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x0)) -#define X64_SRLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x4)) -#define X64_SRAI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x8)) -#define X64_ROTRI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0xc)) -#define X64_RCRI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x10)) -#define X64_ROTLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x14)) -#define X64_RCLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x18)) -#define X64_SLLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x1)) -#define X64_SRLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x5)) -#define X64_SRAI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x9)) -#define X64_ROTRI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0xd)) -#define X64_RCRI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x11)) -#define X64_ROTLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x15)) -#define X64_RCLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x19)) -#define X64_SLLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x2)) -#define X64_SRLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x6)) -#define X64_SRAI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0xa)) -#define X64_ROTRI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0xe)) -#define X64_RCRI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x12)) -#define X64_ROTLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x16)) -#define X64_RCLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x1a)) -#define X64_SLLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x3)) -#define X64_SRLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x7)) -#define X64_SRAI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0xb)) -#define X64_ROTRI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0xf)) -#define X64_RCRI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x13)) -#define X64_ROTLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x17)) -#define X64_RCLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x1b)) +#define X64_INC_B(rj) EMIT(type_2R(0x20, rj, 0x0)) +#define X64_INC_H(rj) EMIT(type_2R(0x20, rj, 0x1)) +#define X64_INC_W(rj) EMIT(type_2R(0x20, rj, 0x2)) +#define X64_INC_D(rj) EMIT(type_2R(0x20, rj, 0x3)) +#define X64_DEC_B(rj) EMIT(type_2R(0x20, rj, 0x4)) +#define X64_DEC_H(rj) EMIT(type_2R(0x20, rj, 0x5)) +#define X64_DEC_W(rj) EMIT(type_2R(0x20, rj, 0x6)) +#define X64_DEC_D(rj) EMIT(type_2R(0x20, rj, 0x7)) +#define X64_MUL_B(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x0)) +#define X64_MUL_H(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x1)) +#define X64_MUL_W(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x2)) +#define X64_MUL_D(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x3)) +#define X64_MUL_BU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x4)) +#define X64_MUL_HU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x5)) +#define X64_MUL_WU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x6)) +#define X64_MUL_DU(rj, rk) EMIT(type_3R(0x7d, rk, rj, 0x7)) +#define X64_ADD_WU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x0)) +#define X64_ADD_DU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1)) +#define X64_SUB_WU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x2)) +#define X64_SUB_DU(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x3)) +#define X64_ADD_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x4)) +#define X64_ADD_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x5)) +#define X64_ADD_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x6)) +#define X64_ADD_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x7)) +#define X64_SUB_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x8)) +#define X64_SUB_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x9)) +#define X64_SUB_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xa)) +#define X64_SUB_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xb)) +#define X64_ADC_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xc)) +#define X64_ADC_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xd)) +#define X64_ADC_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xe)) +#define X64_ADC_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0xf)) +#define X64_SBC_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x10)) +#define X64_SBC_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x11)) +#define X64_SBC_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x12)) +#define X64_SBC_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x13)) +#define X64_SLL_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x14)) +#define X64_SLL_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x15)) +#define X64_SLL_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x16)) +#define X64_SLL_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x17)) +#define X64_SRL_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x18)) +#define X64_SRL_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x19)) +#define X64_SRL_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1a)) +#define X64_SRL_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1b)) +#define X64_SRA_B(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1c)) +#define X64_SRA_H(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1d)) +#define X64_SRA_W(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1e)) +#define X64_SRA_D(rj, rk) EMIT(type_3R(0x7e, rk, rj, 0x1f)) +#define X64_ROTR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x0)) +#define X64_ROTR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x1)) +#define X64_ROTR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x2)) +#define X64_ROTR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x3)) +#define X64_ROTL_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x4)) +#define X64_ROTL_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x5)) +#define X64_ROTL_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x6)) +#define X64_ROTL_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x7)) +#define X64_RCR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x8)) +#define X64_RCR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x9)) +#define X64_RCR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xa)) +#define X64_RCR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xb)) +#define X64_RCL_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xc)) +#define X64_RCL_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xd)) +#define X64_RCL_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xe)) +#define X64_RCL_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0xf)) +#define X64_AND_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x10)) +#define X64_AND_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x11)) +#define X64_AND_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x12)) +#define X64_AND_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x13)) +#define X64_OR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x14)) +#define X64_OR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x15)) +#define X64_OR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x16)) +#define X64_OR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x17)) +#define X64_XOR_B(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x18)) +#define X64_XOR_H(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x19)) +#define X64_XOR_W(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x1a)) +#define X64_XOR_D(rj, rk) EMIT(type_3R(0x7f, rk, rj, 0x1b)) +#define X64_SLLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x0)) +#define X64_SRLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x4)) +#define X64_SRAI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x8)) +#define X64_ROTRI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0xc)) +#define X64_RCRI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x10)) +#define X64_ROTLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x14)) +#define X64_RCLI_B(rj, imm3) EMIT(type_2RI3(0x2a1, imm3, rj, 0x18)) +#define X64_SLLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x1)) +#define X64_SRLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x5)) +#define X64_SRAI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x9)) +#define X64_ROTRI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0xd)) +#define X64_RCRI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x11)) +#define X64_ROTLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x15)) +#define X64_RCLI_H(rj, imm4) EMIT(type_2RI4(0x151, imm4, rj, 0x19)) +#define X64_SLLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x2)) +#define X64_SRLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x6)) +#define X64_SRAI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0xa)) +#define X64_ROTRI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0xe)) +#define X64_RCRI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x12)) +#define X64_ROTLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x16)) +#define X64_RCLI_W(rj, imm5) EMIT(type_2RI5(0xa9, imm5, rj, 0x1a)) +#define X64_SLLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x3)) +#define X64_SRLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x7)) +#define X64_SRAI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0xb)) +#define X64_ROTRI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0xf)) +#define X64_RCRI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x13)) +#define X64_ROTLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x17)) +#define X64_RCLI_D(rj, imm6) EMIT(type_2RI6(0x55, imm6, rj, 0x1b)) // Warning, these are LBT addons that uses LBT4.eflags internally #define ADC_B(rd, rj, rk) EMIT(type_3R(0x60, rk, rj, rd)) |