diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/la64/dynarec_la64_0f.c | 5 | ||||
| -rw-r--r-- | src/dynarec/la64/la64_emitter.h | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/dynarec/la64/dynarec_la64_0f.c b/src/dynarec/la64/dynarec_la64_0f.c index a9909edd..725e7158 100644 --- a/src/dynarec/la64/dynarec_la64_0f.c +++ b/src/dynarec/la64/dynarec_la64_0f.c @@ -220,10 +220,9 @@ uintptr_t dynarec64_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni v1 = sse_get_reg(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 1); VEXTRINS_D(v1, v0, 0x01); } else { - addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 1, 0); + addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 0, 0); v1 = fpu_get_scratch(dyn); - VEXTRINS_D(v1, v0, 0x01); - FST_D(v1, ed, fixedaddress); + VSTELM_D(v0, ed, 0, 1); SMWRITE2(); } break; diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h index 70e28922..cb5393a4 100644 --- a/src/dynarec/la64/la64_emitter.h +++ b/src/dynarec/la64/la64_emitter.h @@ -1428,6 +1428,10 @@ LSX instruction starts with V, LASX instruction starts with XV. #define VEXTRINS_B(vd, vj, imm8) EMIT(type_2RI8(0b01110011100011, imm8, vj, vd)) #define VLD(vd, rj, imm12) EMIT(type_2RI12(0b0010110000, imm12, rj, vd)) #define VST(vd, rj, imm12) EMIT(type_2RI12(0b0010110001, imm12, rj, vd)) +#define VSTELM_D(vd, rj, imm8, imm1) EMIT(type_2RI9(0b0011000100010, (((imm1) << 8) | (imm8)), rj, vd)) +#define VSTELM_W(vd, rj, imm8, imm2) EMIT(type_2RI10(0b001100010010, (((imm2) << 8) | (imm8)), rj, vd)) +#define VSTELM_H(vd, rj, imm8, imm3) EMIT(type_2RI11(0b00110001010, (((imm3) << 8) | (imm8)), rj, vd)) +#define VSTELM_B(vd, rj, imm8, imm4) EMIT(type_2RI12(0b0011000110, (((imm4) << 8) | (imm8)), rj, vd)) #define VLDREPL_D(vd, rj, imm9) EMIT(type_2RI9(0b0011000000010, imm9, rj, vd)) #define VLDREPL_W(vd, rj, imm10) EMIT(type_2RI10(0b001100000010, imm10, rj, vd)) #define VLDREPL_H(vd, rj, imm11) EMIT(type_2RI11(0b00110000010, imm11, rj, vd)) |