diff options
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/dynarec_arm64_66.c | 29 | ||||
| -rwxr-xr-x | src/dynarec/dynarec_arm64_emit_math.c | 99 | ||||
| -rwxr-xr-x | src/dynarec/dynarec_arm64_helper.h | 2 |
3 files changed, 76 insertions, 54 deletions
diff --git a/src/dynarec/dynarec_arm64_66.c b/src/dynarec/dynarec_arm64_66.c index 680d822d..401f80a3 100755 --- a/src/dynarec/dynarec_arm64_66.c +++ b/src/dynarec/dynarec_arm64_66.c @@ -53,8 +53,33 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } switch(opcode) { - - + case 0x01: + INST_NAME("ADD Ew, Gw"); + SETFLAGS(X_ALL, SF_SET); + nextop = F8; + GETGW(x2); + GETEW(x1, 0); + emit_add16(dyn, ninst, x1, x2, x4, x5); + EWBACK; + break; + case 0x03: + INST_NAME("ADD Gw, Ew"); + SETFLAGS(X_ALL, SF_SET); + nextop = F8; + GETGW(x1); + GETEW(x2, 0); + emit_add16(dyn, ninst, x1, x2, x3, x4); + GWBACK; + break; + case 0x05: + INST_NAME("ADD AX, Iw"); + SETFLAGS(X_ALL, SF_PENDING); + i32 = F16; + UXTHw(x1, xRAX); + MOV32w(x2, i32); + emit_add16(dyn, ninst, x1, x2, x3, x4); + BFIx(xRAX, x1, 0, 16); + break; case 0x0F: addr = dynarec64_660F(dyn, addr, ip, ninst, rex, ok, need_epilog); diff --git a/src/dynarec/dynarec_arm64_emit_math.c b/src/dynarec/dynarec_arm64_emit_math.c index 680a68c6..a696f735 100755 --- a/src/dynarec/dynarec_arm64_emit_math.c +++ b/src/dynarec/dynarec_arm64_emit_math.c @@ -494,57 +494,54 @@ void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, in } // emit ADD16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved -//void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4) -//{ -// IFX(X_PEND) { -// STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1)); -// STR_IMM9(s2, xEmu, offsetof(x64emu_t, op2)); -// SET_DF(s3, d_add16); -// } else IFX(X_ALL) { -// SET_DFNONE(s3); -// } -// IFX(X_AF|X_OF|X_PF){if(save_s4) {PUSH(xSP, 1<<s4);}} -// IFX(X_AF | X_OF) { -// ORR_REG_LSL_IMM5(s3, s1, s2, 0); // s3 = op1 | op2 -// AND_REG_LSL_IMM5(s4, s1, s2, 0); // s4 = op1 & op2 -// } -// ADD_REG_LSL_IMM5(s1, s1, s2, 0); -// -// IFX(X_AF|X_OF) { -// BIC_REG_LSL_IMM5(s3, s3, s1, 0); // s3 = (op1 | op2) & ~ res -// ORR_REG_LSL_IMM5(s3, s3, s4, 0); // s3 = (op1 & op2) | ((op1 | op2) & ~ res) -// IFX(X_AF) { -// MOV_REG_LSR_IMM5(s4, s3, 3); -// BFI(xFlags, s4, F_AF, 1); // AF: bc & 0x08 -// } -// IFX(X_OF) { -// MOV_REG_LSR_IMM5(s4, s3, 14); -// XOR_REG_LSR_IMM8(s4, s4, s4, 1); -// BFI(xFlags, s4, F_OF, 1); // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1 -// } -// } -// IFX(X_CF) { -// MOV_REG_LSR_IMM5(s3, s1, 16); -// BFI(xFlags, s3, F_CF, 1); -// } -// IFX(X_PEND) { -// STR_IMM9(s1, xEmu, offsetof(x64emu_t, res)); -// } -// IFX(X_ZF) { -// UXTH(s1, s1, 0); -// TSTS_REG_LSL_IMM5(s1, s1, 0); -// ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0); -// BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0); -// } -// IFX(X_SF) { -// MOV_REG_LSR_IMM5(s3, s1, 15); -// BFI(xFlags, s3, F_SF, 1); -// } -// IFX(X_PF) { -// emit_pf(dyn, ninst, s1, s3, s4); -// } -// IFX(X_AF|X_OF|X_PF){if(save_s4) {POP(xSP, 1<<s4);}} -//} +void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4) +{ + IFX(X_PEND) { + STRH_U12(s1, xEmu, offsetof(x64emu_t, op1)); + STRH_U12(s2, xEmu, offsetof(x64emu_t, op2)); + SET_DF(s3, d_add16); + } else IFX(X_ALL) { + SET_DFNONE(s3); + } + IFX(X_AF | X_OF) { + ORRw_REG(s3, s1, s2); // s3 = op1 | op2 + ANDw_REG(s4, s1, s2); // s4 = op1 & op2 + } + ADDw_REG(s1, s1, s2); + + IFX(X_AF|X_OF) { + BICw_REG(s3, s3, s1); // s3 = (op1 | op2) & ~ res + ORRw_REG(s3, s3, s4); // s3 = (op1 & op2) | ((op1 | op2) & ~ res) + IFX(X_AF) { + LSRw(s4, s3, 3); + BFIw(xFlags, s4, F_AF, 1); // AF: bc & 0x08 + } + IFX(X_OF) { + LSRw(s4, s3, 14); + EORw_REG_LSR(s4, s4, s4, 1); + BFIw(xFlags, s4, F_OF, 1); // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1 + } + } + IFX(X_CF) { + LSRw(s3, s1, 16); + BFIw(xFlags, s3, F_CF, 1); + } + IFX(X_PEND) { + STRH_U12(s1, xEmu, offsetof(x64emu_t, res)); + } + IFX(X_ZF) { + ANDSw_mask(s1, s1, 0, 15); //mask=0xffff + CSETw(s3, cEQ); + BFIw(xFlags, s3, F_ZF, 1); + } + IFX(X_SF) { + LSRw(s3, s1, 15); + BFIw(xFlags, s3, F_SF, 1); + } + IFX(X_PF) { + emit_pf(dyn, ninst, s1, s3, s4); + } +} // emit ADD16 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved //void emit_add16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4) diff --git a/src/dynarec/dynarec_arm64_helper.h b/src/dynarec/dynarec_arm64_helper.h index 016c7896..339f7b05 100755 --- a/src/dynarec/dynarec_arm64_helper.h +++ b/src/dynarec/dynarec_arm64_helper.h @@ -660,7 +660,7 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4) void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4); //void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4); void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4); -//void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4); +void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4); //void emit_add16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4); //void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4); //void emit_sub16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4); |