diff options
Diffstat (limited to 'src')
| -rwxr-xr-x | src/dynarec/arm64_emitter.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h index 709ca4e6..d69e3a71 100755 --- a/src/dynarec/arm64_emitter.h +++ b/src/dynarec/arm64_emitter.h @@ -646,21 +646,21 @@ #define VSHL_16(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0010 | ((shift)>>3)&1, (shift)&7, Vn, Vd)) #define VSHL_32(Vd, Vn, shift) EMIT(SHL_vector(0, 0b0100 | ((shift)>>3)&3, (shift)&7, Vn, Vd)) -#define SHR_vector(Q, U, immh, immb, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b111110<<23 | (immh)<<19 | (immb)<<16 | 0b00000<<11 | 1<<10 | (Rn)<<5 | (Rd)) -#define VSHRQ_8(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0001, (shift)&7, Vn, Vd)) -#define VSHRQ_16(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0010 | ((shift)>>3)&1, (shift)&7, Vn, Vd)) -#define VSHRQ_32(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0100 | ((shift)>>3)&3, (shift)&7, Vn, Vd)) -#define VSHRQ_64(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b1000 | ((shift)>>3)&7, (shift)&7, Vn, Vd)) -#define VSHR_8(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0001, (shift)&7, Vn, Vd)) -#define VSHR_16(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0010 | ((shift)>>3)&1, (shift)&7, Vn, Vd)) -#define VSHR_32(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0100 | ((shift)>>3)&3, (shift)&7, Vn, Vd)) -#define VSSHRQ_8(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0001, (shift)&7, Vn, Vd)) -#define VSSHRQ_16(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0010 | ((shift)>>3)&1, (shift)&7, Vn, Vd)) -#define VSSHRQ_32(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0100 | ((shift)>>3)&3, (shift)&7, Vn, Vd)) -#define VSSHRQ_64(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b1000 | ((shift)>>3)&7, (shift)&7, Vn, Vd)) -#define VSSHR_8(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0001, (shift)&7, Vn, Vd)) -#define VSSHR_16(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0010 | ((shift)>>3)&1, (shift)&7, Vn, Vd)) -#define VSSHR_32(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0100 | ((shift)>>3)&3, (shift)&7, Vn, Vd)) +#define SHR_vector(Q, U, immh, immb, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b011110<<23 | (immh)<<19 | (immb)<<16 | 0b00000<<11 | 1<<10 | (Rn)<<5 | (Rd)) +#define VSHRQ_8(Vd, Vn, shift) EMIT(SHR_vector(1, 1, 0b0001, (8-(shift))&7, Vn, Vd)) +#define VSHRQ_16(Vd, Vn, shift) EMIT(SHR_vector(1, 1, 0b0010 | ((16-(shift))>>3)&1, (16-(shift))&7, Vn, Vd)) +#define VSHRQ_32(Vd, Vn, shift) EMIT(SHR_vector(1, 1, 0b0100 | ((32-(shift))>>3)&3, (32-(shift))&7, Vn, Vd)) +#define VSHRQ_64(Vd, Vn, shift) EMIT(SHR_vector(1, 1, 0b1000 | ((64-(shift))>>3)&7, (64-(shift))&7, Vn, Vd)) +#define VSHR_8(Vd, Vn, shift) EMIT(SHR_vector(0, 1, 0b0001, (8-(shift))&7, Vn, Vd)) +#define VSHR_16(Vd, Vn, shift) EMIT(SHR_vector(0, 1, 0b0010 | ((16-(shift))>>3)&1, (16-(shift))&7, Vn, Vd)) +#define VSHR_32(Vd, Vn, shift) EMIT(SHR_vector(0, 1, 0b0100 | ((32-(shift))>>3)&3, (32-(shift))&7, Vn, Vd)) +#define VSSHRQ_8(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0001, (8-(shift))&7, Vn, Vd)) +#define VSSHRQ_16(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0010 | ((16-(shift))>>3)&1, (16-(shift))&7, Vn, Vd)) +#define VSSHRQ_32(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b0100 | ((32-(shift))>>3)&3, (32-(shift))&7, Vn, Vd)) +#define VSSHRQ_64(Vd, Vn, shift) EMIT(SHR_vector(1, 0, 0b1000 | ((64-(shift))>>3)&7, (64-(shift))&7, Vn, Vd)) +#define VSSHR_8(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0001, (8-(shift))&7, Vn, Vd)) +#define VSSHR_16(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0010 | ((16-(shift))>>3)&1, (16-(shift))&7, Vn, Vd)) +#define VSSHR_32(Vd, Vn, shift) EMIT(SHR_vector(0, 0, 0b0100 | ((32-(shift))>>3)&3, (32-(shift))&7, Vn, Vd)) #define EXT_vector(Q, Rm, imm4, Rn, Rd) ((Q)<<30 | 0b101110<<24 | (Rm)<<16 | (imm4)<<11 | (Rn)<<5 | (Rd)) #define VEXTQ_8(Rd, Rn, Rm, index) EMIT(EXT_vector(1, Rm, index, Rn, Rd)) |