| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | [ARM64_DYNAREC] Fixed an issue when purging an YMM that is used in the same ↵ | ptitSeb | 2024-06-08 | 4 | -0/+16 | |
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| * | Added 2 wrapped function to libglib2 | ptitSeb | 2024-06-08 | 1 | -0/+2 | |
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| * | [RCFILE] Added a few more profiles | ptitSeb | 2024-06-07 | 1 | -0/+12 | |
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| * | Only expose xsave extension if avx is used | ptitSeb | 2024-06-07 | 1 | -2/+2 | |
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| * | [DYNAREC] This should fix RV64 and LA64 builds | ptitSeb | 2024-06-07 | 6 | -4/+12 | |
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| * | [ARM64_DYNAREC] Fixed YMM cache handling, espcially in high pressure regs cases | ptitSeb | 2024-06-07 | 8 | -83/+140 | |
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| * | [RV64_DYNAREC] Fixed sign extension of 8-bit immediate in 66 opcodes (#1568) | xctan | 2024-06-07 | 2 | -10/+10 | |
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| * | [ARM64_DYNAREC] Added BMI.0F38 F2, F3/1 opcodes | ptitSeb | 2024-06-07 | 1 | -0/+46 | |
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| * | [ARM64_DYNAREC] That's just cosmetic... | ptitSeb | 2024-06-07 | 1 | -2/+2 | |
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| * | Wrapped libnettle8 (#1567) | LiZhuoheng | 2024-06-07 | 8 | -0/+187 | |
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| * | [RV64_DYNAREC] Fixed some opcodes caught by cosim (#1561) | xctan | 2024-06-06 | 10 | -97/+130 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Fixed emit_shrd16c * [RV64_DYNAREC] Fixed BSWAP Gw * [RV64_DYNAREC] Fixed 32 bit RCL/RCR Ed, 1 * [RV64_DYNAREC] Fixed 32 bit BTR * [RV64_DYNAREC] Fixed 32 bit SHLD * [RV64_DYNAREC] Fixed 32 bit SHLD again * [RV64_DYNAREC] Fixed 16 bit constant SHLD again * [RV64_DYNAREC] Fixed 16-bit BTC * [RV64_DYNAREC] Fixed 32-bit rotates using Zbb extension * [RV64_DYNAREC] Fixed 16-bit SHLD opcode * [RV64_DYNAREC] Fixed the mask of LAHF opcode * [RV64_DYNAREC] Fixed LAHF again and handled OF2 before cosim * [RV64_DYNAREC] Fixed XADD Eb, Gb when Eb == Gb * [RV64_DYNAREC] Fixed XADD Ew, Gw when Ew == Gw * [RV64_DYNAREC] Fixed zero extension of 32 bit Ed operand * [RV64_DYNAREC] Fixed XADD Eb, Gb again for AH, BH, CH, DH * [RV64_DYNAREC] Fixed various 16-bit immediate extension | |||||
| * | [INTERPRETER] Added suport for F16C extension (linked to AVX flag) ↵ | ptitSeb | 2024-06-06 | 10 | -8/+216 | |
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| * | Disable F16C for now, it's not ready yet | ptitSeb | 2024-06-06 | 1 | -1/+1 | |
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| * | [ARM64_DYNAREC] Added a new small batch of AVX/BMI2 opcodes | ptitSeb | 2024-06-06 | 11 | -10/+208 | |
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| * | [ARM64_DYNAREC] Fixed VCMPSS opcode | ptitSeb | 2024-06-06 | 1 | -0/+50 | |
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| * | Wrapped libtasn1-6 (#1563) | LiZhuoheng | 2024-06-06 | 10 | -0/+104 | |
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| * | Wrapped libp11-kit (#1562) | LiZhuoheng | 2024-06-06 | 8 | -0/+81 | |
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| * | [ARM64_DYNAREC] Added a few more AVX opcodes | ptitSeb | 2024-06-05 | 5 | -8/+138 | |
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| * | Added an AVX test (not on Android, needs to be build there) | ptitSeb | 2024-06-05 | 4 | -0/+1414 | |
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| * | [ARM64_DYNAREC] Added a bunch of AVX ocpodes and some fixes too | ptitSeb | 2024-06-05 | 8 | -89/+301 | |
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| * | [INTERPRETER] Fixed VCMP opcode familly, that needs more cases on than ↵ | ptitSeb | 2024-06-05 | 4 | -55/+116 | |
| | | | | | con-vex CMP familly | |||||
| * | [DYNAREC] Improved handling of the Ymm0 attribute | ptitSeb | 2024-06-05 | 11 | -25/+69 | |
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| * | [ARM64_DYNAREC] Small optim for AVX.66.0F D7 opcode | ptitSeb | 2024-06-05 | 1 | -23/+19 | |
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| * | [LA64_DYNAREC] Fixed LOCK DEC opcode (#1560) | Yang Liu | 2024-06-04 | 1 | -1/+1 | |
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| * | [DYNAREC] Small improvment to Dynarec infrastructure | ptitSeb | 2024-06-04 | 1 | -1/+4 | |
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| * | [ARM64_DYNAREC] Added AVX.0F 16/50/53/C2 opcodes | ptitSeb | 2024-06-03 | 1 | -1/+113 | |
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| * | [LA64_DYNAREC] Added more opcodes (#1558) | Yang Liu | 2024-06-03 | 10 | -2/+447 | |
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| * | [LA64_DYNAREC] Fixed emit_or16 (#1559) | Yang Liu | 2024-06-03 | 1 | -1/+1 | |
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| * | [ARM64_DYNAREC] Added AVX.66.0F 5A/5C-5F/D0-D3 | ptitSeb | 2024-06-03 | 1 | -2/+183 | |
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| * | [ARM64_DYNAREC] Cosmetic change | ptitSeb | 2024-06-03 | 1 | -10/+10 | |
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| * | [ARM64_DYNAREC] Added AVX.66.0F3A 02/08-09/0E/14/20/40/4A-4B opcodes | ptitSeb | 2024-06-03 | 2 | -0/+200 | |
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| * | [INTERPRETER] Fixed name in comment of an opcode | ptitSeb | 2024-06-03 | 1 | -2/+2 | |
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| * | [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1557) | xctan | 2024-06-03 | 2 | -19/+322 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F 38 0B PMULHRSW opcode * [RV64_DYNAREC] Added 0F E4 PMULHUW opcode * [RV64_DYNAREC] Added 0F F4 PMULUDQ opcode * [RV64_DYNAREC] Added 0F F6 PSADBW opcode * [RV64_DYNAREC] Added 0F 38 08 PSIGNB opcode * [RV64_DYNAREC] Optimized 66 0F 38 08 PSIGNB opcode * [RV64_DYNAREC] Added 0F 38 0A PSIGND opcode * [RV64_DYNAREC] Optimized 66 0F 38 0A PSIGND opcode * [RV64_DYNAREC] Added 0F 38 09 PSIGNW opcode * [RV64_DYNAREC] Optimized 66 0F 38 09 PSIGNW opcode * [RV64_DYNAREC] Added 0F F2 PSLLD opcode * [RV64_DYNAREC] Added 0F F3 PSLLQ opcode * [RV64_DYNAREC] Added 0F F1 PSLLW opcode * [RV64_DYNAREC] Fixed 0F F1/F2 PSLLW/PSLLD opcode * [RV64_DYNAREC] Added 0F E1 PSRAW opcode * [RV64_DYNAREC] Added 0F D2 PSRLD opcode * [RV64_DYNAREC] Added 0F D3 PSRLQ opcode * [RV64_DYNAREC] Added 0F D1 PSRLW opcode * [RV64_DYNAREC] Added 0F F8 PSUBB opcode * [RV64_DYNAREC] Added 0F FA PSUBD opcode * [RV64_DYNAREC] Added 0F FB PSUBQ opcode * [RV64_DYNAREC] Added 0F E8 PSUBSB opcode and optimized 0F E9 PSUBSW opcode * [RV64_DYNAREC] Added 0F D8 PSUBUSB opcode | |||||
| * | [ARM64_DYNAREC] Added AVX.66.0F38 ↵ | ptitSeb | 2024-06-03 | 3 | -2/+503 | |
| | | | | | 17/20-25/29/37-40/45-47/78-79/99/AA/AE-AF/BB-BD/F7 opcodes | |||||
| * | [INTERPRETER] Fixed name in comment of an opcode | ptitSeb | 2024-06-03 | 1 | -1/+1 | |
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| * | [ARM64_DYNAREC] Added AVX.66.0F38 19/1A and AVX.66.0F3A 22 opcodes | ptitSeb | 2024-06-03 | 2 | -0/+44 | |
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| * | [ARM64_DYNAREC] Fixed AVX.F2/F3.0F 5D/5F opcodes | ptitSeb | 2024-06-03 | 2 | -18/+10 | |
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| * | [ARM64_DYNAREC] Empty regs needs to be fetched last (again) | ptitSeb | 2024-06-03 | 1 | -42/+14 | |
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| * | [ARM64_DYNAREC] Fixed AVX Cache transform between internal jump points | ptitSeb | 2024-06-03 | 2 | -5/+7 | |
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| * | [COSIM] Added more helpers to avoid segfault on rare cases | ptitSeb | 2024-06-03 | 4 | -8/+11 | |
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| * | [ARM64_DYNAREC] Empty register needs to be fetched last | ptitSeb | 2024-06-03 | 1 | -17/+9 | |
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| * | [INTERPRETER] Fixed VZEROUPPER opcode | ptitSeb | 2024-06-03 | 1 | -1/+1 | |
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| * | Try to fix mmap64 already defined error in custommem.c (#1552) | Romain TISSERAND | 2024-06-03 | 3 | -26/+50 | |
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| * | [ARM64_DYNAREC] Added AVX.F3.0F 52, AVX.66.0F E4 and AVX.0F 52 opcodes | ptitSeb | 2024-06-02 | 3 | -0/+59 | |
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| * | [ARM64_DYNAREC] Added AVX.66.0F38 08-0A/1C-1E/30-35/58/59/90/92/A8/A9/B8/B9 ↵ | ptitSeb | 2024-06-02 | 4 | -5/+366 | |
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| * | [ARM64_DYNAREC] Remove parasite typo to fix build | ptitSeb | 2024-06-02 | 1 | -1/+1 | |
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| * | [INTERPRETER] Added missing FMA opcodes, and fixed some existing ones | ptitSeb | 2024-06-02 | 1 | -12/+156 | |
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| * | [INTERPRETER] Fixed opcode name in comment | ptitSeb | 2024-06-02 | 1 | -3/+3 | |
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| * | [ARM64_DYNAREC] Added AVX.66.0F D6/E5/E7/F5 opcodes | ptitSeb | 2024-06-02 | 1 | -1/+66 | |
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| * | [ARM64_DYNAREC] Added AVX.66.0F3A 00/01/04/05/0A/0B/46 opcodes | ptitSeb | 2024-06-02 | 1 | -0/+126 | |
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