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* [ARM64_DYNAREC] Better handling for invalid opcodesptitSeb2025-10-141-134/+113
* [DYNAREC] Improved Memory Barrier handling for LOCK prefixed opcodesptitSeb2025-09-161-17/+0
* [DYNACACHE] Refactored cpu extension, will be used in dynacache signature checksptitSeb2025-06-141-15/+15
* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-011-2/+1
* [ARM64_DYNAREC] Improved some 66 F0 opcode, especially unaligned pathptitSeb2025-02-121-17/+29
* [DYNAREC] Introduced TO_NAT to ease register mapping changes in future (#2111)Yang Liu2024-12-051-16/+16
* [DYNAREC] Reuse strongmem infra for all backends (#2052)Yang Liu2024-11-211-1/+1
* [ARM64_DYNAREC] Some rework on 8/16/32/64 INC/DEC opcodesptitSeb2024-11-141-2/+2
* [ARM64_DYNAREC] Various small fixes for some 16bits math/logic opcodesptitSeb2024-11-131-2/+1
* [ARM64_DYNAREC] Reworked 8/16/32/64bits XOR opcodesptitSeb2024-11-131-13/+13
* [ARM64_DYNAREC] Fixed previous commitptitSeb2024-11-131-34/+35
* [ARM64_DYNAREC] Reworked 8/16/32/64 OR opcodesptitSeb2024-11-131-5/+13
* [ARM64_DYNAREC] Reworked 8/16/32/64bits AND opcodesptitSeb2024-11-131-6/+14
* [ARM64_DYNAREC] Added 66 F0 01 opcode (for CP2077)ptitSeb2024-02-271-0/+31
* [ARM64_DYNAREC] Added F0 21 opcodeptitSeb2024-02-081-0/+33
* [ARM64_DYNAREC] Improved stability when USCAT extention is supported, qn d im...ptitSeb2024-02-071-6/+24
* [ARM64_DYNAREC] Restaured Memory Barrier on LOCK operation, and disable the u...ptitSeb2023-12-021-1/+13
* [ARM64_DYNAREC] More changes to Strong memory model emulationptitSeb2023-10-181-8/+0
* [ARM64_DYNAREC] Added support for BOX4_DYNAREC_ALIGNED_ATOMICSptitSeb2023-10-171-37/+50
* [ARM64_DYNAREC] More fixes for Atomics extensionptitSeb2023-10-171-3/+3
* [ARM64_DYNAREC] Added code generation for Atomic ARM v8.1 extension for most ...ptitSeb2023-10-161-57/+137
* [ARM64_DYNAREC] Added F0 10/11 opcodeswannacu2023-08-171-1/+22
* [32BTIS][DYNAREC_RV64] Added support for 32bits (#861)Yang Liu2023-06-251-10/+5
* A few cosmetic fixes (#858)Alexandre Julliard2023-06-241-1/+0
* [32BITS][ARM64_DYNAREC] Added 66 F0 prefixed opcodesptitSeb2023-06-241-5/+0
* [32BITS][DYNAREC] Preparing work for 32bits dynarecptitSeb2023-06-231-4/+10
* [ARM64_DYNAREC] Use STUR/LDUR when possible, plus some other small improvmentsptitSeb2023-03-131-12/+13
* [DYNAREC] Various small fixes and improvment on DynarecptitSeb2023-02-161-4/+1
* [DYNAREC] Refactored Strong Memory Model emulationptitSeb2022-11-261-12/+12
* [DYNAREC] Added 66 F0 0F B1 opcodeptitSeb2022-10-281-0/+47
* Added 66 F0 0F C1 opcode ([DYNAREC] too) (for FRAMED Collection on Steam)ptitSeb2022-07-031-0/+37
* [DYNAREC] Add a mecanism to remember fixed address accessed with LOCK, so MOV...ptitSeb2022-07-031-10/+10
* [DYNAREC] Fix an issue with LOCK ADD Ew, Iw opcodeptitSeb2022-05-261-3/+3
* [DYNAREC] Better handling of opcodes with 66 F0 prefixesptitSeb2022-04-171-0/+328