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* [ARM64_DYNAREC] Better handling for invalid opcodesptitSeb2025-10-141-34/+46
* [ARM64_DYNAREC] A few minor fixes to some opcodesptitSeb2025-09-081-24/+16
* [ARM64_DYNAREC] Introduced a dynarec version of the UpdateFlags helper functionptitSeb2025-08-301-1/+1
* [ARM64_DYNAREC] Small optim on (V/F)COMI(SS/SD) opcodesptitSeb2025-07-161-1/+3
* [ARM64_DYNAREC] Added 67 9C opcodeptitSeb2025-06-291-0/+6
* [ARM64_DYNAREC] Improved handling of last_ipptitSeb2025-06-241-0/+1
* [DYNAREC] Refactored a bit BARRIER_FLOAT ([ARM64] olny for now, todo for RV64...ptitSeb2025-06-231-1/+0
* [DYNACACHE] Introduced DynaCache for ARM64 (disabled by default)ptitSeb2025-06-191-1/+1
* [DYNACACHE] More work on dynache relocationptitSeb2025-06-151-0/+1
* [DYNACACHE] Created a const table, for later use in internal relocation ([ARM...ptitSeb2025-06-131-2/+2
* [ARM64_DYNAREC] Added 67 0F 29 opcodeptitSeb2025-04-151-0/+16
* [DYNAREC] Better handling of self-loop and added CALLRET=2 settings (ARM64 on...ptitSeb2025-04-091-2/+10
* Moved more functions to os.h (#2497)Yang Liu2025-04-031-1/+0
* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-011-2/+1
* [ARM64_DYNAREC] Added 67 66 0F 76/EF opcodes (for #1046)ptitSeb2025-03-211-1/+36
* [ARM64_DYNAREC] More work on UD flagsptitSeb2025-02-171-31/+43
* [ARM64_DYNAREC] Continue work on UD flagsptitSeb2025-02-171-10/+18
* [ARM64_DYNAREC] More work on flagptitSeb2025-02-121-25/+23
* [DYNAREC] Added preliminary per-file settings (#2288)Yang Liu2025-01-231-4/+4
* [ENV] Initial refactor of env variables infrastructure (#2274)Yang Liu2025-01-211-8/+8
* [ARM64_DYNAREC] Removed an unused arg in SET_DFNONE (#2266)Yang Liu2025-01-161-7/+7
* [ARM64_DYNAREC] Remove bloated x87 comp codeptitSeb2025-01-081-1/+1
* [ARM64_DYNAREC] Fixed 67 8D opcodeptitSeb2024-12-261-3/+1
* [ARM64_DYNAREC] Reworked MUL/IMUL opcodes a bitptitSeb2024-12-221-9/+23
* [INTERPRETER] Added 64bits 67 A1 opcode ([ARM64_DYNAREC] Too)ptitSeb2024-12-091-0/+10
* [DYNAREC] Introduced TO_NAT to ease register mapping changes in future (#2111)Yang Liu2024-12-051-22/+22
* [ARM64_DYNAREC] Improved some x87 opcode behaviourptitSeb2024-12-021-1/+1
* [ARM64_DYNAREC] Added DYNAREC_PAUSE option for hint instructions (#2070)Yang Liu2024-11-251-3/+5
* [DYNAREC] Reuse strongmem infra for all backends (#2052)Yang Liu2024-11-211-1/+1
* [DYNAREC] Reworked strong memory emulation (#2043)Yang Liu2024-11-191-8/+2
* [ARM64_DYNAREC] Reworked 8/16/32/64bits TEST opcodesptitSeb2024-11-141-4/+2
* [ARM64_DYNAREC] Some refactor on 8/16/32/64bits SHL/SHR/SAR opcodesptitSeb2024-11-141-3/+5
* [ARM64_DYNAREC] Some rework on 8/16/32/64 INC/DEC opcodesptitSeb2024-11-141-2/+2
* [ARM64_DYNAREC] Reworked 8/16/32/64bits XOR opcodesptitSeb2024-11-131-2/+1
* [ARM64_DYNAREC] Reworked 8/16/32/64 OR opcodesptitSeb2024-11-131-2/+1
* [ARM64_DYNAREC] Reworked 8/16/32/64bits AND opcodesptitSeb2024-11-131-2/+1
* [ARM64_DYNAREC] Improved div/idiv opcode flags (non)handlingptitSeb2024-11-131-2/+12
* [ARM64_DYNAREC] Improved 32/64bits imul/mul opcodes flags handlingptitSeb2024-11-131-10/+52
* Added some weird 67 and 64/65 prefixed opcodes ([ARM64_DYNAREC] too)ptitSeb2024-11-071-0/+53
* [ARM64_DYNAREC] Also use Native Carry flags directly when possibleptitSeb2024-10-291-2/+2
* [ARM64_DYNAREC] More work around native flags handlingptitSeb2024-10-201-4/+4
* [DYNAREC] Optimized CALL/RET RAS for out of dynablock jumps (#1909)Yang Liu2024-10-071-4/+11
* [ARM64_DYNAREC] Fixed reset of rex on 67 prefixed opcodesptitSeb2024-09-241-2/+3
* [ARM64_DYNAREC] Added 67 A9 opcode, and fixed 67 opcode with ignored REX prefixptitSeb2024-09-241-0/+9
* [ARM64_DYNAREC] Added 67 66 0F 7E opcodeptitSeb2024-09-041-0/+25
* [ARM64_DYNAREC] Added 67 F3 0F 38 F6 opcode (for #1775)ptitSeb2024-08-301-0/+33
* [ARM64_DYNAREC] Added 67 90..97 opcodesptitSeb2024-08-151-0/+19
* [ARM64_DYNAREC] Some small improvments to ROR/ROL/RCR/RCL opcodesptitSeb2024-08-111-2/+2
* Added 64bits 67 F3 0F 7F opcode ([ARM64_DYNAREC] too)ptitSeb2024-08-101-0/+13
* [DYNAREC] Remove BARRIER_NEXT macroptitSeb2024-07-291-1/+0