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* [DYNAREC] Fixed some oversized memory load (#3051)Yang Liu2025-10-101-1/+6
* [ARM+4_DYNAREC] Fixed (V)[LD/ST]MXCSR opcodes when using SSE_FLUSHTO0ptitSeb2025-07-291-18/+18
* [ARM64_DYNAREC] Small optim on (V/F)COMI(SS/SD) opcodesptitSeb2025-07-161-1/+3
* [ARM64_DYNAREC] Made (V)M(IN/AX)P(D/S) opcodes always exact, it's inexpensive...ptitSeb2025-06-291-20/+8
* [DYNACACHE] More work on preparing internal reloc, plus fix non-trace buildptitSeb2025-06-131-3/+0
* [ARM64_DYNAREC] Fixed a potential issue with (V)STMXCSR opcodesptitSeb2025-04-301-1/+1
* [ARM64_DYNAREC] Small fixes and improvments to (V)MOVMSKP[S/D] opcodesptitSeb2025-04-231-5/+4
* [ARM64_DYNAREC] Few fixes and small cosmetic changes to some partial (V)MOV o...ptitSeb2025-04-231-9/+8
* [ARM64_DYNAREC] Various improvment to various SSE/AVX 128bits/256bits mov op...ptitSeb2025-04-231-23/+33
* [ARM4_DYNAREC] A few changes to seem SSE/AVX comparison and convertions opcod...ptitSeb2025-04-041-1/+1
* Moved more functions to os.h (#2497)Yang Liu2025-04-031-1/+0
* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-011-2/+1
* [ARM64_DYNAREC] Addedfastnan=0 code to (V)SQRTPS opcodesptitSeb2025-03-261-2/+16
* [ARM64_DYNAREC] Improved (V)MAXP[S/D] and (V)MINP[S/D] opcodes to more closel...ptitSeb2025-03-261-8/+12
* [ARM64_DYNAREC] Added missing SMWRITE2 to another AVX opcodeptitSeb2025-03-171-0/+1
* [ARM64_DYNAREC] Fixed a potential issue with AVX.0F 50 opcodeptitSeb2025-03-081-1/+1
* [ARM64_DYNAREC] Various small fixes and optims in a few AVX opcodesptitSeb2025-01-311-11/+11
* [ARM64_DYNAREC] Added experimental synch of fpsr and mxcsr for the flags, whe...ptitSeb2025-01-251-4/+37
* [ARM64_DYNAREC] Added a few AVX opcode and Improved/Fixed some existing SSE a...ptitSeb2025-01-221-28/+96
* [ENV] Initial refactor of env variables infrastructure (#2274)Yang Liu2025-01-211-5/+5
* [ARM64_DYNAREC] Remove bloated x87 comp codeptitSeb2025-01-081-1/+1
* [ARM64_DYNAREC] Improved some x87 opcode behaviourptitSeb2024-12-021-1/+1
* [DYNAREC] Reuse strongmem infra for all backends (#2052)Yang Liu2024-11-211-1/+1
* [ARM64_DYNAREC] Some small optims to a few AVX opcodesptitSeb2024-06-231-2/+15
* [ARM64_DYNAREC] Added AVX.0F 77 256bits opcodeptitSeb2024-06-111-2/+11
* [ARM64_DYNAREC] Fixed AVX.66.0F E1-E3 opcodes and Added AVX.66.0F C6 and AVX....ptitSeb2024-06-111-0/+12
* [ARM64_DYNAREC] That's just cosmetic...ptitSeb2024-06-071-2/+2
* [ARM64_DYNAREC] Added a few more AVX opcodesptitSeb2024-06-051-1/+10
* [ARM64_DYNAREC] Added a bunch of AVX ocpodes and some fixes tooptitSeb2024-06-051-20/+35
* [ARM64_DYNAREC] Added AVX.0F 16/50/53/C2 opcodesptitSeb2024-06-031-1/+113
* [ARM64_DYNAREC] Added AVX.F3.0F 52, AVX.66.0F E4 and AVX.0F 52 opcodesptitSeb2024-06-021-0/+22
* [ARM64_DYNAREC] Added AVX.66.0F3A 21 and fixed a bunch of issuesptitSeb2024-06-021-6/+6
* [ARM64_DYNAREC] Added AVX.0F 28/29/2B/2E/2F/54-56/5A-5F opcodes, plus various...ptitSeb2024-06-011-0/+190
* [ARM64_DYNAREC] Fixed AVX.0F 12/13 opcodesptitSeb2024-05-301-6/+16
* [ARM64_DYNAREC] Added AVX.0F 10-13 opcodesptitSeb2024-05-301-0/+79
* [ARM64_DYNAREC] Added AVX.0F 14/15/77/AE opcodesptitSeb2024-05-301-0/+68
* [ARM64_DYNAREC] Added AVX.0F 58-59 opcodes, and fixed AVX.66.0F3A 18 opcodeptitSeb2024-05-301-0/+20
* [ARM64_DYNAREC] Added AVX.0F 57 opcodeptitSeb2024-05-301-0/+11
* [ARM64_DYNAREC] That first avx opcode now is 256bits enabledptitSeb2024-05-301-6/+33
* [ARM64_DYNAREC] Added a fisrt 128bits only AVX opcodeptitSeb2024-05-301-0/+115