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* [LA64_DYNAREC] Fixed 66 0F 3A 0F PALIGNR for case where dst==src (#2894)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Fixed 66 0F 38 06 PHSUBD opcode (#2893)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Fixed 66 0F 3A 21 INSERTPS opcode (#2891)Yang Liu2025-08-041-6/+4
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* [LA64_DYNAREC] Added and optimized more fastround=0 cases (#2890)Yang Liu2025-08-042-15/+32
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* [LA64_DYNAREC] Fix some la64 ops. (#2889)phorcys2025-08-044-14/+32
| | | | | Fix 0F.BA./7 BTS CF when cpuext.lbt == 1 Fix 66.0F.CF BSWAP 16bits ops. Fix VEXTRACTF128, VINSERTF128
* [LA64_DYNAREC] Fixed 66 0F 38 14 BLENDVPS opcode (#2888)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Fixed 66 0F 3A 0C/0D BLENDPS/D opcodes (#2887)Yang Liu2025-08-041-2/+2
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* [LA64_DYNAREC] Fixed a few GETEX usage (#2886)Yang Liu2025-08-043-44/+44
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* [LA64_DYNAREC] Fixed 0F E2 PSRAD opcode (#2885)Yang Liu2025-08-041-3/+3
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* [LA64_DYNAREC] Fixed 0F E3 PAVGW opcode (#2884)Yang Liu2025-08-041-1/+1
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* [LA64_DYNAREC] Add la64 avx bit ops. (#2873)phorcys2025-08-044-0/+133
| | | | | | * VEX.66.0F.3A VPEXTRB/VPEXTRW/VPEXTRD/VPEXTRQ VPINSRB/VPINSRD/VPINSRQ * VEX.66.0F.C5 VPEXTRW * VEX.66.0f.C4 VPINSRW * VEX.66.0F.38.41 VPHMINPOSUW
* [LA64_DYNAREC] Fix some la64 avx/sse ops. (#2882)phorcys2025-08-026-37/+80
| | | | | | | | | | | | Fix 66.0F.F3 PSLLQ Fix VEX.66.0F.7E VMOVD not zero-extend Fix Vex.66.0F.3A.06 VPERM2F128/VPERM2I128 Fix Vex.66.0F.3A.0D VBLENDPD Fix VEX.66.0F.3A.18/38 VINSERTF128/VINSERTI128 when q0 == q1 or q0 == q2 Fix VEX.66.0F.3A.21 VINSERTPS fix u8 get pos Fix VEX.66.0F.3A.40 VDPPS Fix VREPLVEIxy emit when vex.l Fix VEX.66.0F.38.0C VPERMILPS Fix VEX.66.0F.38.2B VPACKUSDW Fix VEX.66.0F.38.93 VGATHERQPD
* [LA64_DYNAREC] Add la64 avx cvt ops, part 3. (#2869)phorcys2025-08-015-0/+237
| | | | | | | Double <=> Integer convert. Half Float <=> Integer convert. VCVT{DQ2PD, PD2DQ, TPD2DQ} VCVT{SI2SD, SD2SI, TSD2SI} VCVT{PH2PS, PS2PH}
* [INTERP] Try to improve aligned LOCK CMPXCHG8B opcodeptitSeb2025-08-012-0/+17
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* [LA64_DYNAREC] Add la64 avx cvt ops, part2. (#2866)phorcys2025-08-013-0/+158
| | | | | Integer <=> Float convert. VCVT{DQ2PS, PS2DQ, TPS2DQ} VCVT{SI2SS, SS2SI, TSS2SI}
* [LA64_DYNAREC] Add la64 avx cvt ops, part1. (#2859)phorcys2025-07-316-1/+157
| | | | | | Double <=> Float ops, VROUND ops. VCVT{PD2PS,PS2PD, SD2SS, SS2SD} Round{PD,PS,SD,SS}
* [LA64_DYNAREC] Add la64 avx cmp ops, part3. TEST ops. (#2857)phorcys2025-07-304-11/+203
| | | | VPTEST VTESTPD, VTESTPS
* [LA64_DYNAREC] Add la64 avx int cmp ops. (#2856)phorcys2025-07-294-7/+146
| | | | VCMP{EQ,GT}{B,W,D,Q} VCOMISS, VUCOMISS, VCOMISD, VUCOMISD
* [RV64][LA64] Added partial FLUSHTO0 support (#2855)Yang Liu2025-07-292-6/+69
| | | | | | | | | | | * [RV64][LA64] Removed obselete TODOs * more * more * more * more
* [LA64_DYNAREC] Add la64 avx float cmp ops. (#2854)phorcys2025-07-295-17/+132
| | | VCMPPD,VCMPPS,VCMPSD,VCMPSS
* [LA64_DYNAREC] Add la64 avx float ops part 3. (#2845)phorcys2025-07-298-30/+408
| | | | | | | | | * add cpuext.frecipe for LoongArch V1.1 * Fix VFRSQRTE in sse op RSQRTPS/RSQRTSS * Fix VFRECIPE in sse op RCPPS/RCPSS * V{MAX,MIN}{PD,PS,SD,SS} * VRCPPS,VRCPSS * VRSQRTPS,VRSQRTSS * VSQRT{PD,PS,SD,SS}
* [LA64_DYNAREC] Fixed some issue with ADD/SUB x64 eflags when using LBT extensionptitSeb2025-07-241-10/+10
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* Some handling of case where signal numbers differs between native and x64 ↵ptitSeb2025-07-231-2/+2
| | | | archs (not complete, missing sigset conversions)
* [RV64_DYNAREC][LA64_DYNAREC] Simplified defered flags handling and limited ↵Yang Liu2025-07-232-27/+20
| | | | case where UpdateFlags is actualy called (#2844)
* [LA64_DYNAREC] Add la64 avx float ops VDPP{S,D}, VH{ADD,SUB}{PS,PD} (#2842)phorcys2025-07-236-4/+191
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* [LA64_DYNAREC] Add la64 avx float arith ops, part 1. (#2840)phorcys2025-07-225-0/+385
| | | | * V{ADD,SUB,MUL,DIV}{PD,PS,SD,SS} * VADDSUB{PD,PS}
* [LA64_DYNAREC] Add la64 avx FMA insts. (#2838)phorcys2025-07-224-1/+473
| | | | * VF{MADD,MSUB,NMADD,NMSUB}{132,213,231}{PD,PS,SD,SS} * VFM{ADDSUB,SUBADD}{132,213,231}{PD,PS}
* [LA64_DYNAREC] add la64 avx pack/unpack ops, part5. (#2837)phorcys2025-07-213-32/+340
| | | | | | INSERT/EXTRACT/BROADCAST/GATHER ops. VEXTRACTPS,VINSERTPS VBROADCAST{SD,SS}, VPBROADCAST{B,W,D,Q,I128} VPGATHER{DD,DQ,QD,QQ,DPD,DPS,QPD,QPS}
* [DYNAREC] Consolidate access to native register in signal and register ↵ptitSeb2025-07-212-124/+131
| | | | mapping acrross all 3 supported dynarec archs
* [DYNACACHE]LA64] Enabled dynacache for LA64 (#2836)Yang Liu2025-07-215-32/+92
| | | | | * [DYNACACHE]LA64] Enabled dynacache for LA64 * review
* [LA64_DYNAREC] add la64 avx pack/unpack ops, part4. (#2830)phorcys2025-07-218-16/+288
| | | | | | | | | Shuf/Permute ops. VSHUFPS, VSHUFPD VPSHUFD, VPSHUFQ, VPSHUFB, VPSHUFLW, VPSHUFHW VPERMQ, VPERMD VPERMPD, VPERMPS VPERMILPD, VPERMILPS VPERM2F128, VPERM2I128
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 3 blend ops. (#2824)phorcys2025-07-202-3/+228
| | | | | | VBLENDPD, VBLENDPS VPBLENDW, VPBLENDD, VPBLENDVB VBLENDVPD, VBLENDVPS VPALIGNR
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 2. (#2823)phorcys2025-07-183-2/+74
| | | | VUNPCK{LPS,LPD,HPS,HPD} VPUNPCK{LBW,LWD,LDQ,LQDQ,HBW,HWD,HDQ,HQDQ}
* [LA64_DYNAREC] Add la64 avx pack/unpack ops , part 1. (#2818)phorcys2025-07-173-1/+88
| | | | | | VPACKSSWB VPACKSSDW VPACKUSWB VPACKUSDW
* [LA64_DYNAREC] Add la64 avx arith ops, part2. (#2816)phorcys2025-07-154-0/+307
| | | | | * VEX.66.0F VPMADDWD,VPSADBW * VEX.66.0F.38 VPH{ADD,SUB}{W,D,SW}, VPABS{B,W,D} VPMADDUBSW,VPMULHRSW, * VEX.66.0F.3A VMPSADBW
* [LA64_DYNAREC] Optimized PMADDUBSW opcodes (#2817)Yang Liu2025-07-152-25/+18
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* [LA64_DYNAREC] Add la64 avx arith ops , part 1. (#2814)phorcys2025-07-143-6/+357
| | | | | | | | Add 1:1 avx arith ops. * VP{ADD,SUB}{B,W,D,Q,SB,SW,USB,USW} * VPMUL{DQ,,HW,HUW,Lw,LD,LUDQ} * V{MAX,MIN}{UB,UW,UD,SB,SW,SD} * VAVG{B,W} * VSIGN{B,W,D}
* [LA64_DYNAREC] Fix la64 VMASKMOVPS,VMOVHPD. (#2811)phorcys2025-07-142-6/+6
| | | | * fix la64 VMASKMOVPS,VMOVHPD. * fix arm64 VMASKMOVPS,VMASKMOVPD op memo operand order.
* [LA64_DYNAREC] Add la64 avx shift ops. (#2806)phorcys2025-07-143-1/+205
| | | | * VEX.66.0f VPSRLW/VPSRLDVPSRLQ/VPSRAW/VPSRAD/VPSLLW/VPSLLD/VPSLLQ * VEX.66.0f.3a VPSRLVD/VPSRLVQ/VPSRAVDVPSLLVD/VPSLLVQ
* [LA64_DYNAREC] Optimized some SSE shift opcodes (#2813)Yang Liu2025-07-141-58/+38
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* [LA64_DYNAREC] Add la64 avx BMI2 shift ops. (#2807)phorcys2025-07-145-5/+164
| | | | | * VEX.66.0f.38 SHLX * VEX.f2.0f.38 SHRX * VEX.f3.0f.38 SARX
* [LA64_DYNAREC] Add la64 avx shift ops with imm operand. (#2805)phorcys2025-07-112-0/+175
| | | | | | VEX.128/256 66.0F shift imm ops: * 71 VPSRLW/VPSRAW/VPSLLW * 72 VPSRLD/VPSRAD/VPSLLD * 73 VPSRLQ/VPSLLQ/VPSRLDQ/VPSLLDQ
* [LA64_DYNAREC] Fix/Opt la64 avx movsx/movzx ops. (#2804)phorcys2025-07-111-126/+34
| | | | | | Use vext2xv to opt movsx/movzx. For VEX.128 bw,wd,dq ops, use vsllwil(latency 2) instead of vext2xv (latency 3) Old imp use xvsllwil is wrong, because xvsllwil operate on per 128bits channel. But MOVSX/MOVZX VEX.256 ops only read src operand from low 128bits.
* [ARM64_DYNAREC] Simplified defered flags handling and limited case where ↵ptitSeb2025-07-102-4/+1
| | | | UpdateFlags is actualy called (could be simplified more) (TODO on RV64 and LA64)
* [RCFILE] Fixed profile per lib/dll that was using default instead of curent ↵ptitSeb2025-07-091-0/+2
| | | | env for non defined values
* [LA64_DYNAREC] Fix la64 avx->sse same reg migration. (#2801)phorcys2025-07-091-1/+3
| | | | | In current code, if an avx reg writed reg is used by following sse inst. A VLD would emitted by sse_get_reg, causing prev avx inst writed content lose. Skip sse_get_reg's VLD emit, when reg content is already load/changed in prev avx inst.
* [LA64_DYNAREC] Opt/fix la64 avx mov ops. (#2800)phorcys2025-07-093-15/+6
| | | | | | * opt VEX.66.0F.D6 VMOVD * opt VEX.F2.0F.10 VMOSD * opt VEX.F3.0F.10 VMOVSS * opt/fix VEX.F3.0F.7E VMOVD
* [LA64_DYNAREC] Add la64 avx bitwise ops. (#2780)phorcys2025-07-097-33/+305
| | | | | | | * avx VEX.66.0F 54/55/56/57 VANDPD/VANDNPD/VORPD/VXORPD * avx VEX.0F 54/55/56/57 VANDPS/VANDNPS/VORPS/VXORPS * avx VEX.66.0F DB/DF/EB/EF VPAND/VPANDN/VPOR/VPXOR * bmi1 VEX.0F38 F2 ANDN * bmi2 VEX.F2.0F3A F0 RORX
* [LA64_DYNAREC] Fix VEX.0f.17 VMOVHPS, one break missing. (#2798)phorcys2025-07-051-0/+1
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* [DYNAREC] Fixed a potential issue where defered flags are not computed/reset ↵ptitSeb2025-07-021-1/+1
| | | | on internal jump