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* [LA64_DYNAREC] Added unaligned F0 81/83 /0,5 LOCK ADD/SUB opcodes (#3084)Yang Liu2025-10-211-16/+37
| | | | | * [LA64_DYNAREC] Added unaligned F0 81/83 /5 LOCK SUB opcodes * add too
* [LA64_DYNAREC] Added a few more opcodes (#3081)Yang Liu2025-10-214-1/+170
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* [LA64] Fixed LBT signal handling, also refined la64noext support (#3080)Yang Liu2025-10-221-0/+12
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* [LA64_DYNAREC] Added more opcodes (#3079)Yang Liu2025-10-191-0/+19
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* [LA64_DYNAREC] Added x87 support (#3078)Yang Liu2025-10-1919-30/+3384
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* [COSIM] Disable tests fo CD opcodeptitSeb2025-10-161-0/+1
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* [LA64_DYNAREC] Fix SSE CMPPD, wrong reg operand for cUN cOR. (#3068)phorcys2025-10-141-2/+2
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* Added preliminary unit test runner (#3045)Yang Liu2025-10-141-7/+14
| | | | | | | | | | | | | | | | | * Added preliminary unit test runner * Set .text section address * Added support for added custom memory regions * Move json.h to include * Display banner * Added support for custom memory data * Added the ability to include path in nasm * Print env variables
* [LA64_DYNAREC] Fixed BEXTR opcode (#3067)Yang Liu2025-10-131-2/+2
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* [LA64_DYNAREC] Fixed non-lbt path INC/DEC opcodes register conflicts (#3066)Yang Liu2025-10-131-21/+27
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* [LA64_DYNAREC] Fixed some oversized load (#3065)Yang Liu2025-10-132-4/+8
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* [DYNAREC] Fixed negative issues with 0F/F0 A3/AB/B3/BB opcodes (#3057)Yang Liu2025-10-111-4/+16
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* [DYNAREC] Fixed some oversized memory load (#3051)Yang Liu2025-10-102-4/+12
| | | | | * [DYNAREC] Fixed some oversized memory load * review
* [DYNAREC] Fixed 66 8D opcode and also a regression introduced in last commit ↵Yang Liu2025-10-101-1/+1
| | | | (#3050)
* [DYNAREC][INTERP] Fixed an edge case of CMPXHG (#3049)Yang Liu2025-10-101-5/+10
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* [DYNAREC] Fixed a special case of SHLD/SHRD opcodes (#3047)Yang Liu2025-10-102-3/+8
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* [DYNAREC][INTERP] Added a few multibyte nops (#3046)Yang Liu2025-10-102-0/+10
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* [LA64_DYNAREC] Refactor register mapping (#2940)Leslie Zhai2025-09-1916-248/+317
| | | | | | | | | | | | | * [LA64_DYNAREC] Refactor register mapping * [LA64_DYNAREC] Fix typo * [LA64_DYNAREC] Remapping xSavedSP to fp ($r22) * [LA64_DYNAREC] Fix VPCLMULQDQ x3 and x4 issue * [LA64_DYNAREC] Fix typo * [LA64_DYNAREC] Fix typo
* [LA64_DYNAREC] Fixed AVX 0F 17 VMOVHPS opcode (#3025)Yang Liu2025-09-171-1/+1
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* [LA64_DYNAREC] Fixed AVX 66 0F 67 PACKUSWB opcode (#3024)Yang Liu2025-09-171-1/+1
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* [LA64_DYNAREC] Fixed avx infra (#3023)Yang Liu2025-09-171-2/+2
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* [DYNAREC] Improved Memory Barrier handling for LOCK prefixed opcodesptitSeb2025-09-163-32/+0
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* [DYNAREC] Small refactor on StrongMem emulator and lock prefixptitSeb2025-09-132-2/+1
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* [INTERP][DYNAREC] Aligned !fastnan handling of 0F 51/52 opcodes (#2989)Yang Liu2025-09-011-1/+11
| | | | | | | | | * [INTERP] Added !fastnan handling to some 0F opcodes * [RV64_DYNAREC] Fixed/refined !fastnan handling of some 0F opcodes * la64 * more fixes
* [LA64_DYNAREC] Fixed a typo in 0F 53 RCPPS opcode (#2991)Yang Liu2025-09-011-4/+3
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* [LA64_DYNAREC] Fix 0f.A3 BT opcode, fix ALSL operand order. (#2988)phorcys2025-09-011-1/+1
| | | | | ALSL.D: tmp = (GR[rj][63:0]<<(sa2+1)) + GR[rk][63:0] GR[rd] = tmp[63:0]
* [LA64_DYNAREC] Fixed AVX VCVT[T]PS2DQ fastround path (#2979)Yang Liu2025-08-293-11/+19
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* [RV64_DYNAREC] Added more scalar avx opcodes (#2978)Yang Liu2025-08-291-1/+1
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* [RV64_DYNAREC] Added more scalar avx opcodes (#2961)Yang Liu2025-08-211-1/+1
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* [LA64_DYNAREC] Add la64 BMI/BMI2 ops. (#2933)phorcys2025-08-153-2/+233
| | | | | VEX.0F.38 BLSR, BLSMSK, BLSI, BZHI, BEXTR VEX.F2.0F.38 PDEP, MULX VEX.F3.0F.38 PEXT
* [DYNAREC] Fixed reading emu->df (#2936)Yang Liu2025-08-152-13/+13
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* [LA64_DYNAREC] Fix VMOVNTDQA. (#2934)phorcys2025-08-152-16/+16
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* [LA64_DYNAREC] Add la64 avx insts using helpers. (#2935)phorcys2025-08-152-22/+168
| | | | VEX.66.0F.38 VAESIMC, VAESENC, VAESENCLAST, VAESDEC, VAESDECLAST VEX.66.0F.3a VPCLMULQDQ, VAESKEYGENASSIST
* [LA64_DYNAREC] Fixed a typo in CMPXCHG8B opcode (#2931)Yang Liu2025-08-131-1/+1
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* [DYNAREC] Rearranged arch-specific AVX infra code (#2930)Yang Liu2025-08-131-5/+0
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* [LA64_DYNAREC] Fix B3 BTR eflags when cpuext.lbt == 1. Fix 16bits AND when ↵phorcys2025-08-122-2/+6
| | | | cpuext.lbt == 1. (#2929)
* [RV64_DYNAREC][LA64_DYNAREC] Fixed missing zeroup in geted_32() (#2921)Yang Liu2025-08-081-0/+1
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* [LA64_DYNAREC] Fixed AVX VPMOVMSKB opcode (#2920)Yang Liu2025-08-071-2/+2
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* [LA64_DYNAREC] Fixed AVX VPERM2F128/VPERM2I128 opcodes (#2919)Yang Liu2025-08-071-1/+1
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* [LA64_DYNAREC] Fixed AVX VMASKMOVDQU opcode (#2918)Yang Liu2025-08-071-1/+1
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* [LA64_DYNAREC] Fixed AVX VPBLENDW opcodes (#2917)Yang Liu2025-08-071-18/+6
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* [LA64_DYNAREC] Fixed AVX VMOVMSKPS/VMOVMSKPD opcodes (#2916)Yang Liu2025-08-072-4/+4
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* [LA64_DYNAREC] Fixed AVX VMOVSS opcode (#2915)Yang Liu2025-08-071-1/+1
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* [LA64_DYNAREC] Fixed AVX VCMPSS/VCMPSD opcodes (#2914)Yang Liu2025-08-072-2/+4
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* [LA64_DYNAREC] Fixed some AVX scalar MIN/MAX opcodes (#2913)Yang Liu2025-08-072-5/+5
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* [LA64_DYNAREC] Refined F3 0F 5D/5F MINSS/MAXSS opcodes (#2912)Yang Liu2025-08-071-18/+16
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* [LA64_DYNAREC] Fixed 66 0F 3A 16 PEXTRD opcode (#2906)Yang Liu2025-08-061-1/+1
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* [LA64_DYNAREC] Fixed 66 F3 0F B8 POPCNT opcode (#2905)Yang Liu2025-08-061-4/+5
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* [LA64_DYNAREC] Added more opcodes (#2902)Yang Liu2025-08-066-1/+248
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* [LA64_DYNAREC] Fixed F3 0F 53 RCPSS opcode (#2892)Yang Liu2025-08-041-7/+3
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