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* [DYNAREC] Fixed getX64Address empty block handling (#3085)Yang Liu2025-10-221-0/+1
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* [LA64_DYNAREC] Added unaligned F0 81/83 /0,5 LOCK ADD/SUB opcodes (#3084)Yang Liu2025-10-211-16/+37
| | | | | * [LA64_DYNAREC] Added unaligned F0 81/83 /5 LOCK SUB opcodes * add too
* [DYNAREC] Fixed native_fprem/native_fprem1 (fixed the camera issue of ↵Yang Liu2025-10-211-35/+12
| | | | FlatOut/FlatOut2) (#3083)
* [RV64_DYNAREC] Added DB /2 FIST opcode (#3082)Yang Liu2025-10-212-2/+18
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* [LA64_DYNAREC] Added a few more opcodes (#3081)Yang Liu2025-10-214-1/+170
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* [LA64] Fixed LBT signal handling, also refined la64noext support (#3080)Yang Liu2025-10-221-0/+12
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* [DYNAREC] Reversing b40cb7b84a1a404a0d2b042791d9133bde3f1b77 as it generate ↵ptitSeb2025-10-202-13/+4
| | | | tons of regression and it tries to fix a non-issue
* [LA64_DYNAREC] Added more opcodes (#3079)Yang Liu2025-10-191-0/+19
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* [LA64_DYNAREC] Added x87 support (#3078)Yang Liu2025-10-1920-32/+3384
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* [COSIM] Disable tests fo CD opcodeptitSeb2025-10-163-1/+3
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* [DYNAREC] Fixed potential issue with signel not being re-enabled after ↵ptitSeb2025-10-162-4/+13
| | | | FillBlock64 got canceled in a signal handler
* [ARM64_DYNAREC] Better handling for invalid opcodesptitSeb2025-10-147-881/+842
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* [LA64_DYNAREC] Fix SSE CMPPD, wrong reg operand for cUN cOR. (#3068)phorcys2025-10-141-2/+2
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* Added preliminary unit test runner (#3045)Yang Liu2025-10-143-14/+50
| | | | | | | | | | | | | | | | | * Added preliminary unit test runner * Set .text section address * Added support for added custom memory regions * Move json.h to include * Display banner * Added support for custom memory data * Added the ability to include path in nasm * Print env variables
* [LA64_DYNAREC] Fixed BEXTR opcode (#3067)Yang Liu2025-10-131-2/+2
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* [LA64_DYNAREC] Fixed non-lbt path INC/DEC opcodes register conflicts (#3066)Yang Liu2025-10-131-21/+27
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* [LA64_DYNAREC] Fixed some oversized load (#3065)Yang Liu2025-10-132-4/+8
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* [RV64_DYNAREC] Fixed some 16bit BT/BTS/BTR/BTC opcodes (#3062)Yang Liu2025-10-121-47/+135
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* [ARM64_DYNAREC] Fixed a typo in iret_to_epilog (#3059)Yang Liu2025-10-121-1/+1
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* [DYNAREC] Fixed negative issues with 0F/F0 A3/AB/B3/BB opcodes (#3057)Yang Liu2025-10-113-10/+40
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* [RV64_DYNAREC] Fixed some missing sse_forget_reg for implicit xmm0 (#3056)Yang Liu2025-10-111-0/+4
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* [RV64_DYNAREC] Fixed a typo in 16bit ROR/ROL opcodes (#3053)Yang Liu2025-10-111-5/+4
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* [DYNAREC] Fixed some oversized memory load (#3051)Yang Liu2025-10-107-14/+48
| | | | | * [DYNAREC] Fixed some oversized memory load * review
* [ARM64_DYNAREC] Changed BSF/BSR to not changed Ed if Gd==0 (seems current ↵ptitSeb2025-10-101-4/+0
| | | | cpu does this)
* [DYNAREC] Fixed 66 8D opcode and also a regression introduced in last commit ↵Yang Liu2025-10-104-10/+8
| | | | (#3050)
* [DYNAREC][INTERP] Fixed an edge case of CMPXHG (#3049)Yang Liu2025-10-104-25/+43
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* [ARM64_DYNAREC] Don't assume x1 is xRIP in link_next (fix regression ↵ptitSeb2025-10-101-0/+1
| | | | introduced with 685afa230291d64f350afbfdfa8fc82536d99f82)
* [DYNAREC] Fixed a special case of SHLD/SHRD opcodes (#3047)Yang Liu2025-10-106-9/+24
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* [DYNAREC][INTERP] Added a few multibyte nops (#3046)Yang Liu2025-10-107-0/+35
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* [ARM64_DYNAREC] Use UDF for UD2 & unsupported WBINVDptitSeb2025-10-071-6/+2
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* [DYNAREC] Optimized scalar AES impl in DynaRec (#3041)xctan2025-10-052-20/+180
| | | | | | | | | | | | | * [DYNAREC] Optimized scalar AES impl * [RV64_DYNAREC] Optimized AES with RVV * [CI] Bump RISC-V toolchains * [RV64_DYNAREC] Switch to scalar impl when xtheadvector is present * [RV64_DYNAREC] Try to disable rvv aes kernels * [RV64_DYNAREC] Reverted assembly aes functions
* [DYNAREC] Fixe a speed regression introduced with ↵ptitSeb2025-10-031-7/+2
| | | | 3fe020572dfc0636ab82bae962c3514134e9e128 (for #3038)
* [ARM64_DYNAREC] Small improvment on some invalid opcode handlingptitSeb2025-10-012-2/+38
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* [TRACE] Added tooling to check if x86/x64 opcode is validptitSeb2025-10-011-1/+8
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* [ARM64_DYNAREC] Improved IRET handling of boggus parametersptitSeb2025-09-295-18/+44
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* [RV64_DYNAREC] Added more scalar avx opcodes (#3037)Yang Liu2025-09-293-3/+419
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* [RV64_DYNAREC] Fixed a scratch register confliction (#3033)Yang Liu2025-09-271-1/+1
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* [ARM64_DYNAREC] Added more variant of INS/OUT opcodesptitSeb2025-09-242-1/+77
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* [ARM64_DYNAREC] Fixed flags for 8bits imulptitSeb2025-09-241-2/+3
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* RV64_DYNAREC] Added more avx scalar opcodes (#3029)Yang Liu2025-09-223-2/+58
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* [RV64_DYNAREC] Added more avx scalar opcodes (#3028)Yang Liu2025-09-221-0/+93
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* [LA64_DYNAREC] Refactor register mapping (#2940)Leslie Zhai2025-09-1916-248/+317
| | | | | | | | | | | | | * [LA64_DYNAREC] Refactor register mapping * [LA64_DYNAREC] Fix typo * [LA64_DYNAREC] Remapping xSavedSP to fp ($r22) * [LA64_DYNAREC] Fix VPCLMULQDQ x3 and x4 issue * [LA64_DYNAREC] Fix typo * [LA64_DYNAREC] Fix typo
* [ARM64_DYNAREC] Temporarily disable Atomic path for F0 0F B1, as it avoid ↵ptitSeb2025-09-171-2/+5
| | | | some games random freeze (like HorizonZeroDawn or Cyberpunk2077)
* [LA64_DYNAREC] Fixed AVX 0F 17 VMOVHPS opcode (#3025)Yang Liu2025-09-171-1/+1
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* [ARM64_DYNAREC] Fixed non-Atomic path for F0 0F C0 opcodeptitSeb2025-09-171-4/+4
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* [LA64_DYNAREC] Fixed AVX 66 0F 67 PACKUSWB opcode (#3024)Yang Liu2025-09-171-1/+1
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* [LA64_DYNAREC] Fixed avx infra (#3023)Yang Liu2025-09-171-2/+2
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* [DYNAREC] Improved Memory Barrier handling for LOCK prefixed opcodesptitSeb2025-09-1613-172/+6
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* [ARM64_DYNAREC] Allow use of Native flags when using UFLAG_IF macro helperptitSeb2025-09-152-0/+6
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* [DYNAREC][TRACE] Show if will run Inter or Dynarec when using LongJump to ↵ptitSeb2025-09-141-1/+1
| | | | resume emulation after signal