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* [ARM64_DYNAREC] Made REP MOVSB optimisation flaglessptitSeb2025-04-231-4/+4
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* [ARM64_DYNAREC] Optimized REP STOSBptitSeb2025-04-232-2/+36
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* [ARM64_DYNAREC] Various improvment to various SSE/AVX 128bits/256bits mov ↵ptitSeb2025-04-238-89/+144
| | | | opcodes
* [DYNAREC] Added a x87pc test and some cosmetic changes too (#2561)Yang Liu2025-04-2216-158/+83
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* [LA64_DYNAREC] Add SSSE3's mmx ops. (#2559)phorcys2025-04-221-0/+162
| | | | | | | | | | | | | | | | | 0f.38.00 PSHUFB 01 PHADDW 02 PHADDD 03 PHADDSW 04 PMADDUBSW 05 PHSUBW 06 PHSUBD 07 PHSUBSW 08 PSIGNB 09 PSIGNW 0a PSIGND 0b PMULHRSW 1c PABSB 1d PABSW 1e PABSD
* [ARM64_DYNAREC] Improved (V)[MIN/MAX][S/P][S/D] opcodesptitSeb2025-04-224-34/+10
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* [RV64_DYNAREC] Better handling of x87double=2 (#2560)Yang Liu2025-04-2210-1/+47
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* [ARM64_DYNAREC] Small improvements to (V)MASKMOVDQU opcodeptitSeb2025-04-212-6/+4
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* [ARM64_DYNAREC] Better handling of x87double=2ptitSeb2025-04-2110-0/+53
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* [ARM64_DYNAREC] Fixed potential issue with (V)LDDQU opcodeptitSeb2025-04-212-3/+3
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* [DYNAREC] More handling of low precision x87 flag change (#2556)Yang Liu2025-04-214-2/+8
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* [RV64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and ↵Yang Liu2025-04-211-1/+1
| | | | cosim scenario (#2555)
* [ARM64_DYNAREC] Add/Improved (V)H[ADD/SUB]P[S/D] opcodesptitSeb2025-04-216-23/+53
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* [ARM64_DYNAREC] Small change to 66 0F 3A 17 opcodeptitSeb2025-04-211-2/+2
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* [ARM64_DYNAREC] Minor cosmetic changesptitSeb2025-04-212-2/+2
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* [RV64_DYNAREC] Added X87DOUBLE=2 support (#2553)Yang Liu2025-04-2122-24/+88
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* [ARM64_DYNAREC] Another potential fix for X87DOUBLE=2ptitSeb2025-04-211-1/+1
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* [ARM64_DYNAREC] Fixed some potential issues with BOX64_DYNAREC_DOUBLE=2ptitSeb2025-04-213-4/+1
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* [DYNAREC][TRACE] Slightly better trace message on creating dynablockptitSeb2025-04-181-2/+2
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* [LA64_DYNAREC]Add/opt more SSE/MMX ops (#2543)phorcys2025-04-182-24/+60
| | | | | | | | | | * Add SSE2 op MASKMOVDQU. * Opt PSADBW. * Add SSE3 HSUBPD op. * Add mmx PALIGNR op. * Fix PSRLDQ. * Fix PSRAW Gx,Ex PSRAW Gm,Em. mmx/sse get COUNT from Em/Ex as an 64bit unsigned... testsuite with shift 0x4,0x4,0x4,0x4, result COUNT as 0x04040404.
* [DYNAREC] Small improvment to callret=2 handling of path to regen a blockptitSeb2025-04-181-0/+2
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* [WOW64] Finished skeleton code for PE build (#2542)Yang Liu2025-04-172-2/+0
| | | | | * [WOW64] Finished skeleton code for PE build * move musl to external
* [LA64_DYNAREC] Add SSE1/SSE2's cvt mmx ops. (#2538)phorcys2025-04-172-0/+166
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* [ARM64_DYNAREC] More handling of low precision x87 flag changeptitSeb2025-04-163-0/+4
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* [DYNAREC] Introduce BOX64_DYNAREC_X87DOUBLE=2 to handle Low Precision x87 ↵ptitSeb2025-04-1617-21/+114
| | | | ([ARM64_DYNAREC] only for now)
* [LA64_DYNAREC] Add mmx pack/unpack ops. (#2536)phorcys2025-04-161-9/+83
| | | | | add PUNPCKL{BW,WD,DQ}, PUNPCKH{BW,WD,DQ} mmx ops. add PACKSSWB PACKUSWB PACKSSDW mmx ops. * fix some merge mistake in prev mmx commit.
* [ARM64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and ↵ptitSeb2025-04-151-1/+1
| | | | cosim scenario
* [ARM64_DYNAREC][TRACE] Changed TBZ/TBNZ printer to print bit offset in decimalptitSeb2025-04-151-2/+2
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* [ARM64_DYNAREC] Added 67 0F 29 opcodeptitSeb2025-04-152-0/+41
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* [DYNAREC] Fix on strongmem mode were last write on a seq on 1 write could be ↵ptitSeb2025-04-151-1/+4
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* [LA64_DYNAREC] Add mmx cmp ops. (#2533)phorcys2025-04-151-0/+41
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* [RV64_DYNAREC] fix MASKMOVQ. (#2531)phorcys2025-04-141-1/+1
| | | | | maskmovq write when sign bit == 1. if mask byte = 0x00, should skip. replace BLT with BLE.
* [LA64_DYNAREC] Add mmx arith ops. (#2530)phorcys2025-04-141-0/+71
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* [LA64_DYNAREC] Add mmx shift ops. (#2529)phorcys2025-04-141-0/+148
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* [WOW64] More tweaks for PE build (#2528)Yang Liu2025-04-1410-22/+71
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* [LA64_DYNAREC] Optimize sse_setround (#2527)phorcys2025-04-141-10/+3
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* [LA64_DYNAREC] Add mmx related mov op (#2526)phorcys2025-04-144-15/+102
| | | | | * [LA64_DYNAREC] Add SSE2's MOVQ2DQ/MOVDQ2Q mmx op * [LA64_DYNAREC] Add mmx mov ops.
* [LA64_DYNAREC] Update la64 mmx infra. (#2524)phorcys2025-04-124-55/+846
| | | Co-authored-by: phorcys <phorcys02@126.com>
* [WOW64] Splitted freq and cleanup functions from x64emu (#2521)Yang Liu2025-04-113-4/+4
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* [ARM64_DYNAREC] Some more FRINTTS and AVX/SSE fixes (might help #2520)ptitSeb2025-04-115-30/+22
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* [DYNAREC] Speedup a bit DYNAREC_DIRTY=1ptitSeb2025-04-102-13/+24
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* [WOW64] More tweaks towards PE build (#2519)Yang Liu2025-04-106-13/+13
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* [WOW64] More work on the PE wow64 build (#2518)Yang Liu2025-04-106-12/+10
| | | | | * [WOW64] More work on the PE wow64 build * added a TODO
* [DYNAREC] Improved handling of db_size rbtreeptitSeb2025-04-091-16/+7
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* [DYNAREC] Better handling of self-loop and added CALLRET=2 settings (ARM64 ↵ptitSeb2025-04-0915-19/+151
| | | | only, RV64 and LA64 todo)
* Moved emit functions to seperate files from signals.h (#2516)Yang Liu2025-04-091-0/+1
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* [ARM64_DYNAREC] Fixed some dangling else warnings (#2514)Yang Liu2025-04-091-6/+18
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* [WOW64] Add wow64 PE build scaffolding (#2513)Yang Liu2025-04-081-2/+0
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* [DYNAREC] Do not mark a dynablock as always_test for loop on itself that are ↵ptitSeb2025-04-081-6/+10
| | | | not alive
* [ARM4_DYNAREC] A few changes to seem SSE/AVX comparison and convertions ↵ptitSeb2025-04-048-154/+287
| | | | opcodes, and more FRINTTS usage too