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* [ARM64_DYNAREC] Fixed another issue with Ymm0 mask and reset_cache on ↵ptitSeb2024-06-111-2/+2
| | | | internal jump
* [ARM64_DYNAREC] Added AVX.66.0F38 90/92 opcodes and added AVX.66.0F38 04 opcodeptitSeb2024-06-101-5/+32
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* [ARM64_DYNAREC] Fixed AVX.66.0F3A 00/01 opcodesptitSeb2024-06-101-4/+6
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* [ARM64_DYNAREC] Fixed 256bits version of AVX.66.0F D1/D2/D3 opcodesptitSeb2024-06-101-15/+21
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* [ARM64_DYNAREC] Cosmetic changeptitSeb2024-06-101-1/+0
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* [ARM64_DYNAREC] Fixed an issue when not purging Ymm0 on internal jump with ↵ptitSeb2024-06-091-8/+8
| | | | less Ymm0
* [ARM64_DYNAREC] Fixed AVX.66.0F38 28 opcodeptitSeb2024-06-091-1/+1
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* [ARM64_DYNAREC] Fixed AVX.66.0F 7F opcodeptitSeb2024-06-091-2/+2
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* [DYNAREC] Another fix for YMM Zero'd upper reg trackingptitSeb2024-06-099-45/+55
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* [ARM64_DYNAREC] Added AVX.66.0F38 41/8E/9B, AVX.66.0F3A 06 and AVX.66.0F F6 ↵ptitSeb2024-06-084-0/+156
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* [ARM64_DYNAREC] Another fix for YMM selection on High registry pressure casesptitSeb2024-06-083-17/+44
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* [ARM64_DYNAREC] Added AVX.66.0F 50/C2, AVX.66.0F3A 0D, AVX.66.0F38 ↵ptitSeb2024-06-086-3/+228
| | | | 16/28/29/2B/36/AC/BA and AVX.F2.0F 51 opcodes
* [ARM64_DYNAREC] Small optim on 66 0F 50 opcodeptitSeb2024-06-081-5/+4
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* [ARM64_DYNAREC] Added AVX.66.0F E6, AVX.66.0F38 98 and fixed AVX.F2.0F E6 ↵ptitSeb2024-06-083-6/+61
| | | | opcodes
* [ARM64_DYNAREC] Fixed an issue when purging an YMM that is used in the same ↵ptitSeb2024-06-084-0/+16
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* [DYNAREC] This should fix RV64 and LA64 buildsptitSeb2024-06-076-4/+12
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* [ARM64_DYNAREC] Fixed YMM cache handling, espcially in high pressure regs casesptitSeb2024-06-078-83/+140
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* [RV64_DYNAREC] Fixed sign extension of 8-bit immediate in 66 opcodes (#1568)xctan2024-06-072-10/+10
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* [ARM64_DYNAREC] Added BMI.0F38 F2, F3/1 opcodesptitSeb2024-06-071-0/+46
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* [ARM64_DYNAREC] That's just cosmetic...ptitSeb2024-06-071-2/+2
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* [RV64_DYNAREC] Fixed some opcodes caught by cosim (#1561)xctan2024-06-0610-97/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Fixed emit_shrd16c * [RV64_DYNAREC] Fixed BSWAP Gw * [RV64_DYNAREC] Fixed 32 bit RCL/RCR Ed, 1 * [RV64_DYNAREC] Fixed 32 bit BTR * [RV64_DYNAREC] Fixed 32 bit SHLD * [RV64_DYNAREC] Fixed 32 bit SHLD again * [RV64_DYNAREC] Fixed 16 bit constant SHLD again * [RV64_DYNAREC] Fixed 16-bit BTC * [RV64_DYNAREC] Fixed 32-bit rotates using Zbb extension * [RV64_DYNAREC] Fixed 16-bit SHLD opcode * [RV64_DYNAREC] Fixed the mask of LAHF opcode * [RV64_DYNAREC] Fixed LAHF again and handled OF2 before cosim * [RV64_DYNAREC] Fixed XADD Eb, Gb when Eb == Gb * [RV64_DYNAREC] Fixed XADD Ew, Gw when Ew == Gw * [RV64_DYNAREC] Fixed zero extension of 32 bit Ed operand * [RV64_DYNAREC] Fixed XADD Eb, Gb again for AH, BH, CH, DH * [RV64_DYNAREC] Fixed various 16-bit immediate extension
* [INTERPRETER] Added suport for F16C extension (linked to AVX flag) ↵ptitSeb2024-06-063-0/+77
| | | | ([ARM64_DYNAREC] too)
* [ARM64_DYNAREC] Added a new small batch of AVX/BMI2 opcodesptitSeb2024-06-067-9/+199
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* [ARM64_DYNAREC] Fixed VCMPSS opcodeptitSeb2024-06-061-0/+50
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* [ARM64_DYNAREC] Added a few more AVX opcodesptitSeb2024-06-055-8/+138
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* [ARM64_DYNAREC] Added a bunch of AVX ocpodes and some fixes tooptitSeb2024-06-058-89/+301
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* [DYNAREC] Improved handling of the Ymm0 attributeptitSeb2024-06-0511-25/+69
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* [ARM64_DYNAREC] Small optim for AVX.66.0F D7 opcodeptitSeb2024-06-051-23/+19
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* [LA64_DYNAREC] Fixed LOCK DEC opcode (#1560)Yang Liu2024-06-041-1/+1
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* [DYNAREC] Small improvment to Dynarec infrastructureptitSeb2024-06-041-1/+4
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* [ARM64_DYNAREC] Added AVX.0F 16/50/53/C2 opcodesptitSeb2024-06-031-1/+113
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* [LA64_DYNAREC] Added more opcodes (#1558)Yang Liu2024-06-0310-2/+447
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* [LA64_DYNAREC] Fixed emit_or16 (#1559)Yang Liu2024-06-031-1/+1
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* [ARM64_DYNAREC] Added AVX.66.0F 5A/5C-5F/D0-D3ptitSeb2024-06-031-2/+183
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* [ARM64_DYNAREC] Cosmetic changeptitSeb2024-06-031-10/+10
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* [ARM64_DYNAREC] Added AVX.66.0F3A 02/08-09/0E/14/20/40/4A-4B opcodesptitSeb2024-06-032-0/+200
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* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1557)xctan2024-06-032-19/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F 38 0B PMULHRSW opcode * [RV64_DYNAREC] Added 0F E4 PMULHUW opcode * [RV64_DYNAREC] Added 0F F4 PMULUDQ opcode * [RV64_DYNAREC] Added 0F F6 PSADBW opcode * [RV64_DYNAREC] Added 0F 38 08 PSIGNB opcode * [RV64_DYNAREC] Optimized 66 0F 38 08 PSIGNB opcode * [RV64_DYNAREC] Added 0F 38 0A PSIGND opcode * [RV64_DYNAREC] Optimized 66 0F 38 0A PSIGND opcode * [RV64_DYNAREC] Added 0F 38 09 PSIGNW opcode * [RV64_DYNAREC] Optimized 66 0F 38 09 PSIGNW opcode * [RV64_DYNAREC] Added 0F F2 PSLLD opcode * [RV64_DYNAREC] Added 0F F3 PSLLQ opcode * [RV64_DYNAREC] Added 0F F1 PSLLW opcode * [RV64_DYNAREC] Fixed 0F F1/F2 PSLLW/PSLLD opcode * [RV64_DYNAREC] Added 0F E1 PSRAW opcode * [RV64_DYNAREC] Added 0F D2 PSRLD opcode * [RV64_DYNAREC] Added 0F D3 PSRLQ opcode * [RV64_DYNAREC] Added 0F D1 PSRLW opcode * [RV64_DYNAREC] Added 0F F8 PSUBB opcode * [RV64_DYNAREC] Added 0F FA PSUBD opcode * [RV64_DYNAREC] Added 0F FB PSUBQ opcode * [RV64_DYNAREC] Added 0F E8 PSUBSB opcode and optimized 0F E9 PSUBSW opcode * [RV64_DYNAREC] Added 0F D8 PSUBUSB opcode
* [ARM64_DYNAREC] Added AVX.66.0F38 ↵ptitSeb2024-06-033-2/+503
| | | | 17/20-25/29/37-40/45-47/78-79/99/AA/AE-AF/BB-BD/F7 opcodes
* [ARM64_DYNAREC] Added AVX.66.0F38 19/1A and AVX.66.0F3A 22 opcodesptitSeb2024-06-032-0/+44
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* [ARM64_DYNAREC] Fixed AVX.F2/F3.0F 5D/5F opcodesptitSeb2024-06-032-18/+10
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* [ARM64_DYNAREC] Empty regs needs to be fetched last (again)ptitSeb2024-06-031-42/+14
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* [ARM64_DYNAREC] Fixed AVX Cache transform between internal jump pointsptitSeb2024-06-032-5/+7
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* [ARM64_DYNAREC] Empty register needs to be fetched lastptitSeb2024-06-031-17/+9
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* [ARM64_DYNAREC] Added AVX.F3.0F 52, AVX.66.0F E4 and AVX.0F 52 opcodesptitSeb2024-06-023-0/+59
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* [ARM64_DYNAREC] Added AVX.66.0F38 08-0A/1C-1E/30-35/58/59/90/92/A8/A9/B8/B9 ↵ptitSeb2024-06-024-5/+366
| | | | opcodes
* [ARM64_DYNAREC] Remove parasite typo to fix buildptitSeb2024-06-021-1/+1
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* [ARM64_DYNAREC] Added AVX.66.0F D6/E5/E7/F5 opcodesptitSeb2024-06-021-1/+66
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* [ARM64_DYNAREC] Added AVX.66.0F3A 00/01/04/05/0A/0B/46 opcodesptitSeb2024-06-021-0/+126
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* [ARM64_DYNAREC] Fixed handling of YMM0 on forward jumpptitSeb2024-06-023-3/+7
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* [ARM64_DYNAREC] Added AVX.66.0F 60-63/67-6A/71 opcodesptitSeb2024-06-021-4/+163
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