about summary refs log tree commit diff stats
path: root/src/dynarec (follow)
Commit message (Collapse)AuthorAgeFilesLines
...
* [ARM64_DYNAREC] Don't use fix scratch for x87 conversion, it might conflict ↵ptitSeb2024-06-023-17/+36
| | | | with YMM handling
* [ARM64_DYNAREC] Fixed YMM COSIM refreshing on each stepsptitSeb2024-06-021-3/+3
|
* [LA64_DYNAREC] Added more opcodes (#1549)Yang Liu2024-06-029-0/+654
| | | | | * [LA64_DYNAREC] Added more opcodes * fastnan handling and fixed PALIGNR...
* [ARM64_DYNAREC] Added AVX.66.0F3A 21 and fixed a bunch of issuesptitSeb2024-06-025-21/+62
|
* [LA64_DYNAREC] Added more opcodes and fixed ADC opcode (#1548)Yang Liu2024-06-013-19/+67
|
* [ARM64_DYNAREC] Added AVX.F2.0F 58-5A/5C-5F opcodesptitSeb2024-06-011-0/+123
|
* [ARM64_DYNAREC] Added AVX.66.0F C4/C5/D7 opcodesptitSeb2024-06-012-0/+81
|
* [ARM64_DYNAREC] Added BMI.F2.0F38 F7 opcodeptitSeb2024-06-011-0/+9
|
* [ARM64_DYNAREC] Added AVX.66.0F 10-17/29/29/2B/2E/2F/54-59/74-76/7E opcodesptitSeb2024-06-012-2/+325
|
* [ARM64_DYNAREC] Added AVX.0F 28/29/2B/2E/2F/54-56/5A-5F opcodes, plus ↵ptitSeb2024-06-013-7/+201
| | | | various small fixes
* [INTERP] Rework on the 16b emulation for LA64 (#1547)Yang Liu2024-06-013-20/+3
| | | | | * [INTERP] Rework on the 16b emulation for LA64 * fix compiler issue
* [ARM64_DYNAREC] Added AVX.F3.0F 10-12/16/2A/2C/2D/58-5F opcodes, plus a few ↵ptitSeb2024-06-015-5/+297
| | | | other fixes
* [ARM64_DYNAREC] Added AVX.F2.0F 10-12/2A/2C/2D opcodesptitSeb2024-06-014-5/+203
|
* [ARM64_DYNAREC] Added a few 67 prefixed opcodesptitSeb2024-06-013-0/+175
|
* [ARM64_DYNAREC] Added ADX RORX opcodeptitSeb2024-06-013-0/+81
|
* [ARM64_DYNAREC] Added AVX.66.0F3A 38/39 opcodesptitSeb2024-06-011-2/+4
|
* [ARM64_DYNAREC] Added AVX.66.0F 72/7F/F8-FEptitSeb2024-06-012-0/+162
|
* [ARM64_DYNAREC] Added AVX.F3.0F 7E opcodeptitSeb2024-06-011-0/+15
|
* [ARM64_DYNAREC] Added AVX.66.0F38 00/DC-DF opcodesptitSeb2024-06-013-21/+256
|
* [ARM64_DYNAREC] Fix issue with 66 0F 38 DC-DF when rare case of dest==srcptitSeb2024-06-011-8/+24
|
* [ARM64_DYNAREC] Added AVX.F3.0F 7F opcodeptitSeb2024-06-011-1/+24
|
* [ARM64_DYNAREC] Added a couple of AVX.66.0F3A opcodes, and fixed some ↵ptitSeb2024-06-016-4/+145
| | | | sse/avx function helpers
* [ARM64_DYNAREC] Added some AVX.66.0F opcodesptitSeb2024-06-012-1/+308
|
* [LA64_DYNAREC] Added LOCK CMPXCHG unaligned version (#1545)Yang Liu2024-06-012-3/+24
|
* [RV64_DYNAREC] Fixed LOCK CMPXCHG unaligned version (#1544)Yang Liu2024-06-011-4/+4
|
* [LA64_DYNAREC] Fixed 0F C2 CMPPS opcode (#1543)Yang Liu2024-05-311-8/+8
|
* [ARM64_DYNAREC] Added a bunch of AVX/BMI2/ADX opcodesptitSeb2024-05-318-20/+456
|
* [ARM64_DYNAREC] Some fixes to AVX opcodesptitSeb2024-05-315-10/+17
|
* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1542)xctan2024-05-313-15/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F 38 06 PHSUBD opcode * [RV64_DYNAREC] Added 0F 38 07 PHSUBSW opcode * [RV64_DYNAREC] Added 0F 38 05 PHSUBW opcode * [RV64_DYNAREC] Added 0F C4 PINSRW opcode * [RV64_DYNAREC] Added 0F 38 04 PMADDUBSW opcode * [RV64_DYNAREC] Added 0F EE PMAXSW opcode * [RV64_DYNAREC] Optimized SSE packed min/max * [RV64_DYNAREC] Added 0F DE PMAXUB opcode * [RV64_DYNAREC] Added 0F EA PMINSW opcode * [RV64_DYNAREC] Added 0F DA PMINUB opcode * [RV64_DYNAREC] Optimized 0F D9 PSUBUSW opcode * [RV64_DYNAREC] Added 0F D7 PMOVMSKB opcode * [RV64_DYNAREC] Optimized (66) 0F D7 PMOVMSKB opcode * [RV64_DYNAREC] Switched to the simpler implementation for PMOVMSKB
* [ARM64_DYNBAREC] Added AVX.66.0F38 2C-2F opcodesptitSeb2024-05-304-1/+87
|
* [ARM64_DYNAREC] Added AVX.66.0F 64-66 opcodesptitSeb2024-05-301-0/+31
|
* [ARM64_DYNAREC] Fixed AVX.0F 12/13 opcodesptitSeb2024-05-301-6/+16
|
* [ARM64_DYNAREC] Added AVX.0F 10-13 opcodesptitSeb2024-05-301-0/+79
|
* [ARM64_DYNAREC] Added AVX.0F 14/15/77/AE opcodesptitSeb2024-05-301-0/+68
|
* [ARM64_DYNAREC] Added AVX.66.0F3A 15/16/17 opcodesptitSeb2024-05-301-0/+52
|
* [ARM64_DYNAREC] Added AVX.66.0F 6B opcodeptitSeb2024-05-301-0/+28
|
* [ARM64_DYNAREC] Added AVX.66.F3A 19 opcodes and some various avx helper fixesptitSeb2024-05-304-5/+36
|
* [ARM64_DYNAREC] Added AVX.66.0F 5B/6F opcodesptitSeb2024-05-303-4/+166
|
* [RV64_DYNAREC] Fixed buildptitSeb2024-05-301-1/+1
|
* [ARM64_DYNAREC] Added AVX.0F 58-59 opcodes, and fixed AVX.66.0F3A 18 opcodeptitSeb2024-05-303-4/+24
|
* [ARM64_DYNAREC] Added AVX.66.0F38 18 and AVX.66.0F3A 0C opcodesptitSeb2024-05-305-0/+150
|
* [ARM64_DYNAREC] Added AVX.0F 57 opcodeptitSeb2024-05-302-0/+37
|
* [ARM64_DYNAREC] Added AVX.66.0F3A 18 opcodeptitSeb2024-05-304-1/+98
|
* [ARM64_DYNAREC] That first avx opcode now is 256bits enabledptitSeb2024-05-3026-313/+582
|
* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1539)xctan2024-05-303-60/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F DF PANDN opcode * [RV64_DYNAREC] Added 0F E0 PAVGB opcode * [RV64_DYNAREC] Added 0F E3 PAVGW opcode * [RV64_DYNAREC] Added 0F 74 PCMPEQB opcode * [RV64_DYNAREC] Added 0F 76 PCMPEQD opcode * [RV64_DYNAREC] Added 0F 64 PCMPGTB opcode * [RV64_DYNAREC] Added 0F 66 PCMPGTD opcode and optimized 66 0F 66 PCMPGTD opcode * [RV64_DYNAREC] Added 0F 65 PCMPGTW opcode * [RV64_DYNAREC] Added 0F C5 PEXTRW opcode * [RV64_DYNAREC] Added 0F 38 02 PHADDD opcode * [RV64_DYNAREC] Optimized packed saturate add/sub * [RV64_DYNAREC] Added 0F 38 03 PHADDSW opcode * [RV64_DYNAREC] Added 0F 38 01 PHADDW opcode
* [ARM64_DYNAREC] Added a fisrt 128bits only AVX opcodeptitSeb2024-05-3018-19/+359
|
* Added more MMX opcodes and some optimizations too (#1537)xctan2024-05-302-22/+110
| | | | | | | * [RV64_DYNAREC] Added 0F DD PADDUSW opcode and optimized 66 0F DD PADDUSW opcode * [RV64_DYNAREC] Added 0F 3A 0F PALIGNR opcode * [RV64_DYNAREC] Optimized 66 0F 3A 0F PALIGNR opcode
* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1535)xctan2024-05-284-21/+187
| | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F F7 MASKMOVQ opcode * [RV64_DYNAREC] Added 0F 38 1C PABSB opcode * [RV64_DYNAREC] Added 0F 38 1E PABSD opcode * [RV64_DYNAREC] Added 0F 38 1D PABSW opcode * [RV64_DYNAREC] Added 0F 63 PACKSSWB opcode * [RV64_DYNAREC] Added 0F FC PADDB opcode * [RV64_DYNAREC] Added 0F D4 PADDQ opcode * [RV64_DYNAREC] Added 0F EC PADDSB opcode and optimized 66 0F EC PADDSB opcode * [RV64_DYNAREC] Added 0F DC PADDUSB opcode and optimized 66 0F DC PADDUSB opcode
* [ARM64_DYNAREC] Added faked 0F C7 /4 opcode to get bigger dynablockptitSeb2024-05-271-1/+6
|
* [ARM64_DYNAREC] Fixed some SHA1 opcode when source is same as destptitSeb2024-05-271-5/+6
|