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* [RV64_DYNAREC] Optimize push/pop with xtheadmemidx (#2150)Yang Liu2024-12-131-28/+98
* [RV64_DYNAREC] Fixed some TO_NAT usages (#2149)Yang Liu2024-12-131-4/+4
* [RV64_DYNAREC] Reinitialize sew after callret (#2148)Yang Liu2024-12-131-27/+14
* [RV64_DYNAREC] Reworked ZEROUP and freed t0 (#2147)xctan2024-12-1214-80/+74
* [RV64_DYNAREC] New register mapping (#2139)Yang Liu2024-12-1223-595/+596
* [LA64_DYNAREC] Added more opcodes (#2145)Leslie Zhai2024-12-123-0/+64
* [ARM64_DYNAREC] Force flags to be at least defered when priv opcode is run on...ptitSeb2024-12-113-15/+75
* [DYNAREC] Small improvments on flags when end of block if trigger earlyptitSeb2024-12-112-5/+4
* [ARM64_DYNAREC] Better hadnling of flags on btx opcode familly ([COSIM] and i...ptitSeb2024-12-113-50/+222
* [COSIM] Try to get more stable result on x87 stacks by unwinding status befor...ptitSeb2024-12-118-1/+44
* [LA64_DYNAREC] Added more 660F opcodes (#2127)Leslie Zhai2024-12-103-1/+248
* [INTERPRETER] Added 64bits 67 A1 opcode ([ARM64_DYNAREC] Too)ptitSeb2024-12-091-0/+10
* [LA64_DYNAREC] Added AES opcodes (#2122)Leslie Zhai2024-12-071-0/+76
* [DYNAREC] Fixed a typo which leads to regression (#2121)Yang Liu2024-12-061-1/+1
* [LA64_DYNAREC] Added XOR AX, Iw opcode (#2116)Leslie Zhai2024-12-061-0/+9
* [RV64_DYNAREC] Improve native flag handlingptitSeb2024-12-067-39/+68
* [LA64_DYNAREC] Added HLT opcode (#2112)Leslie Zhai2024-12-051-0/+11
* [NON4KPAGE] Some more adjustments for non-4Kpagesize system (should help #2110)ptitSeb2024-12-051-3/+3
* [DYNAREC] Introduced TO_NAT to ease register mapping changes in future (#2111)Yang Liu2024-12-0567-3960/+4558
* Disable another execution test when pagesize is not 4KptitSeb2024-12-041-2/+2
* Improved signal handling ([BOX32] Too)ptitSeb2024-12-031-4/+4
* [LA64_DYNAREC] Fixed sign extension of 8-bit immediate in 66 opcodes (#2106)Yang Liu2024-12-031-19/+19
* [RV64_DYNAREC] Added simple opcodes fusion as "native flags" (#2102)Yang Liu2024-12-0232-798/+1166
* [ARM64_DYNAREC] Improved some x87 opcode behaviourptitSeb2024-12-0216-45/+99
* [LA64_DYNAREC] Added INSB, INSD, OUTSB and OUTSD opcodes (#2100)Leslie Zhai2024-12-021-0/+24
* *[ARM64_DYNAREC] Fixed some cases of memory access on BTR/BTS opcodes (for #2...ptitSeb2024-12-012-4/+4
* [ARM64_DYNAREC] Added F2 0F 80..8F opcodesptitSeb2024-11-301-0/+37
* Added a new memExist helper function and use it instead of getMmapped were it...ptitSeb2024-11-302-2/+4
* [INTERPRETER] Added 0F 30 ocpode ([RM64_DYNAREC] too) (for #2090)ptitSeb2024-11-301-1/+11
* [RV64] Added nan propagation emulation for interpreter and DynaRec (#2091)Yang Liu2024-11-284-125/+76
* [RV64_DYNAREC] Fix PTEST X_CF typo (#2088)Leslie Zhai2024-11-281-1/+1
* [LA64_DYNAREC] Added LEA opcode (#2087)Leslie Zhai2024-11-281-0/+11
* [RV64_DYNAREC] Fixed another regression in vector (#2086)Yang Liu2024-11-271-2/+2
* [RV64_DYNAREC] Fixed more regressions for vector (#2082)Yang Liu2024-11-262-6/+6
* [ARM64_DYNAREC][TRACE] Use BLR on ret/retn with TRACE to allow relevant debug...ptitSeb2024-11-261-0/+8
* [LA64_DYNAREC] Added SBB opcodes (#2076)Leslie Zhai2024-11-265-1/+115
* [RV64_DYNAREC] Fixed vector packed logical shift opcodes (#2075)xctan2024-11-262-3/+8
* [RV64_DYNAREC] Fixed vector SSE unpack opcodes (#2074)xctan2024-11-251-4/+4
* [ARM64_DYNAREC] Added DYNAREC_PAUSE option for hint instructions (#2070)Yang Liu2024-11-258-7/+34
* [LA64_DYNAREC] Add adc8, adc8c, adc16 and testadc (#2069)Leslie Zhai2024-11-256-0/+293
* [ARM64_DYNAREC] Use YIELD instead of WFE (#2066)Yang Liu2024-11-243-1/+15
* [RV64_DYNAREC] Added, fixed, and optimized opcodes (#2059)xctan2024-11-245-119/+188
* [ARM64_DYNAREC] Fix a regression, as 90 opcode is not always NOP depending on...ptitSeb2024-11-241-12/+14
* [ARM64_DYNAREC] Generate corresponding hint instruction for PAUSE (#2063)Yang Liu2024-11-242-9/+13
* [RV64_DYNAREC] Minor optimizations on CMPXCHG (#2062)Yang Liu2024-11-241-9/+3
* [ARM64_DYNAREC] Small optim for emit_shld32c CF flag computationptitSeb2024-11-231-2/+1
* [DYNAREC] Better detection of wait slotptitSeb2024-11-231-0/+15
* Small fix for XSAVE/XRSTOR opcodes ([DYNAREC] too)ptitSeb2024-11-213-6/+6
* [LA64_DYNAREC] Added more opcodes for JDK (#2055)Yang Liu2024-11-215-1/+272
* [DYNAREC] Reuse strongmem infra for all backends (#2052)Yang Liu2024-11-21105-636/+302