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* [RV64_DYNAREC] Added more MMX opcodes for vector (#2027)xctan2024-11-132-1/+79
* [ARM64_DYNAREC] Reworked 8/16/32/64bits XOR opcodesptitSeb2024-11-136-84/+63
* [ARM64_DYNAREC] Fixed previous commitptitSeb2024-11-133-46/+47
* [ARM64_DYNAREC] Reworked 8/16/32/64 OR opcodesptitSeb2024-11-136-76/+62
* [ARM64_DYNAREC] Reworked 8/16/32/64bits AND opcodesptitSeb2024-11-136-98/+94
* [ARM64_DYNAREC] Small change in sbb32 helperptitSeb2024-11-131-1/+1
* [ARM64_DYNAREC] Improved div/idiv opcode flags (non)handlingptitSeb2024-11-134-12/+60
* [RV64_DYNAREC] Prefer AMO* instructions over LR/SC when possible (#2028)Yang Liu2024-11-134-123/+87
* [ARM64_DYNAREC] Improved 32/64bits imul/mul opcodes flags handlingptitSeb2024-11-134-100/+184
* [RV64_DYNAREC] Added more MMX opcodes for vector (#2026)xctan2024-11-131-0/+131
* [RV64_DYNAREC] Added more MMX opcodes for vector (#2024)xctan2024-11-134-9/+103
* [RV64_DYNAREC] Made eflags emulation branchless with xtheadcondmov (#2019)Yang Liu2024-11-1112-446/+295
* [RV64_DYNAREC] Added more MMX opcodes for vector (#2017)Yang Liu2024-11-113-4/+43
* [ARM64_DYNAREC] A small optim for a specific case of 0F C6 opcodeptitSeb2024-11-091-0/+2
* [DYNAREC] Only test page protection when needed (and using a fester way) (sho...ptitSeb2024-11-091-4/+12
* [RV64_DYNAREC] Added mmx infra for vector (#2011)Yang Liu2024-11-097-54/+185
* [RV64_DYNAREC] Fixed some GETEX_vector usage (#2008)Yang Liu2024-11-081-3/+3
* Added some weird 67 and 64/65 prefixed opcodes ([ARM64_DYNAREC] too)ptitSeb2024-11-072-0/+88
* Added 64/65 69 opcode ([ARM64_DYNAREC] too)ptitSeb2024-11-071-0/+73
* [ARM64_DYNAREC] Fixed some issue with frintts usesptitSeb2024-11-051-2/+2
* [ARM64_DYNAREC] Fixed newly added frrintts useptitSeb2024-11-051-2/+2
* [ARM64_DYNAREC] Reworked a bit FASTROUNDptitSeb2024-11-052-33/+45
* [RV64_DYNAREC] Added more SSE opcodes for vector (#1999)Yang Liu2024-11-051-0/+25
* Improve handling of memory protection, and excution bitptitSeb2024-11-042-1/+4
* [DYNAREC] Reverted last 2 commit, will use CancelFillblock mecanism insteadptitSeb2024-11-036-131/+61
* [LA64_DYNAREC] This should fix Loongarch dynarecptitSeb2024-11-031-0/+11
* [DYNAREC] Make sure the emu structure is up-to-date each time LinkNext is calledptitSeb2024-11-036-61/+120
* [ARM64_DYNAREC] Fixed an issue with native flags and opcode using C Helper th...ptitSeb2024-11-031-5/+5
* [RV64_DYNAREC] Added more opcodes for vector (#1992)Yang Liu2024-11-012-0/+39
* [RV64_DYNAREC] Added more opcodes for vector (#1991)Yang Liu2024-11-013-1/+67
* [RV64_DYNAREC] Added more opcodes for vector (#1989)Yang Liu2024-11-013-0/+78
* [RV64_DYNAREC] Added more opcodes for vector (#1987)Yang Liu2024-10-312-0/+125
* Added 65 6C..6F opcodes ([ARM64_DYNAREC] too) (for #1985)ptitSeb2024-10-311-0/+24
* [RV64_DYNAREC] Added more opcodes for vector (#1983)Yang Liu2024-10-302-0/+57
* [Rv64_DYNAREC] Added more opcodes for vector (#1982)Yang Liu2024-10-302-0/+39
* [RV64_DYNAREC] Added more opcodes for vector (#1981)Yang Liu2024-10-304-20/+109
* [RV64_DYNAREC] Added more opcodes for vector (#1980)Yang Liu2024-10-303-22/+149
* [RV64_DYNAREC] Added more opcodes for vector (#1979)Yang Liu2024-10-292-0/+72
* [RV64_DYNAREC] Added more opcodes for vector (#1978)Yang Liu2024-10-292-2/+80
* [ARM64_DYNAREC] Make sure neg on 16bits is correctly computedptitSeb2024-10-291-2/+3
* [ARM64_DYNAREC] Fixed a potential issue with native flags used while some int...ptitSeb2024-10-291-0/+5
* [ARM64_DYNAREC] Also use Native Carry flags directly when possibleptitSeb2024-10-2913-257/+443
* [RV64_DYNAREC] Fixed 66 0F C2 CMPPD opcode for scalar and more (#1975)Yang Liu2024-10-295-10/+10
* [RV64_DYNAREC] Fixed MAXSS and MAXSD for vector (#1974)Yang Liu2024-10-282-12/+4
* [RV64_DYNAREC] Added more opcodes for vector (#1972)Yang Liu2024-10-282-3/+119
* [RV64_DYNAREC] Added more opcodes for vector (#1970)Yang Liu2024-10-284-31/+266
* [RV64_DYNAREC] Added more opcodes for vector (#1969)Yang Liu2024-10-282-38/+81
* [RV64_DYNAREC] Added more opcodes for vector (#1968)Yang Liu2024-10-283-47/+159
* [RV64_DYNAREC] Added more opcodes for vector (#1966)Yang Liu2024-10-274-6/+76
* [RV64_DYNAREC] Implemented the first AVX128 opcode for scalar only (#1962)Yang Liu2024-10-268-12/+368