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* *[ARM64_DYNAREC] Fixed some cases of memory access on BTR/BTS opcodes (for #2...ptitSeb2024-12-012-4/+4
* [ARM64_DYNAREC] Added F2 0F 80..8F opcodesptitSeb2024-11-301-0/+37
* Added a new memExist helper function and use it instead of getMmapped were it...ptitSeb2024-11-302-2/+4
* [INTERPRETER] Added 0F 30 ocpode ([RM64_DYNAREC] too) (for #2090)ptitSeb2024-11-301-1/+11
* [RV64] Added nan propagation emulation for interpreter and DynaRec (#2091)Yang Liu2024-11-284-125/+76
* [RV64_DYNAREC] Fix PTEST X_CF typo (#2088)Leslie Zhai2024-11-281-1/+1
* [LA64_DYNAREC] Added LEA opcode (#2087)Leslie Zhai2024-11-281-0/+11
* [RV64_DYNAREC] Fixed another regression in vector (#2086)Yang Liu2024-11-271-2/+2
* [RV64_DYNAREC] Fixed more regressions for vector (#2082)Yang Liu2024-11-262-6/+6
* [ARM64_DYNAREC][TRACE] Use BLR on ret/retn with TRACE to allow relevant debug...ptitSeb2024-11-261-0/+8
* [LA64_DYNAREC] Added SBB opcodes (#2076)Leslie Zhai2024-11-265-1/+115
* [RV64_DYNAREC] Fixed vector packed logical shift opcodes (#2075)xctan2024-11-262-3/+8
* [RV64_DYNAREC] Fixed vector SSE unpack opcodes (#2074)xctan2024-11-251-4/+4
* [ARM64_DYNAREC] Added DYNAREC_PAUSE option for hint instructions (#2070)Yang Liu2024-11-258-7/+34
* [LA64_DYNAREC] Add adc8, adc8c, adc16 and testadc (#2069)Leslie Zhai2024-11-256-0/+293
* [ARM64_DYNAREC] Use YIELD instead of WFE (#2066)Yang Liu2024-11-243-1/+15
* [RV64_DYNAREC] Added, fixed, and optimized opcodes (#2059)xctan2024-11-245-119/+188
* [ARM64_DYNAREC] Fix a regression, as 90 opcode is not always NOP depending on...ptitSeb2024-11-241-12/+14
* [ARM64_DYNAREC] Generate corresponding hint instruction for PAUSE (#2063)Yang Liu2024-11-242-9/+13
* [RV64_DYNAREC] Minor optimizations on CMPXCHG (#2062)Yang Liu2024-11-241-9/+3
* [ARM64_DYNAREC] Small optim for emit_shld32c CF flag computationptitSeb2024-11-231-2/+1
* [DYNAREC] Better detection of wait slotptitSeb2024-11-231-0/+15
* Small fix for XSAVE/XRSTOR opcodes ([DYNAREC] too)ptitSeb2024-11-213-6/+6
* [LA64_DYNAREC] Added more opcodes for JDK (#2055)Yang Liu2024-11-215-1/+272
* [DYNAREC] Reuse strongmem infra for all backends (#2052)Yang Liu2024-11-21105-636/+302
* [ARM64_DYNAREC] More optimizations on strongmem emulation (#2051)Yang Liu2024-11-202-42/+43
* [ARM64_DYNAREC] Added weakbarrier=2 to disable last write barriers (#2049)Yang Liu2024-11-191-15/+15
* [ARM64_DYNAREC] Re-enable weakbarrier for dmb.ishst (#2048)Yang Liu2024-11-191-4/+13
* [DYNAREC] Reworked strong memory emulation (#2043)Yang Liu2024-11-1916-200/+571
* Improved Signal handling ([ARM4_DYNAREC] too)ptitSeb2024-11-182-3/+8
* [ARM64_DYNAREC] Only propagate native flags if at least 1 opcode consume themptitSeb2024-11-171-7/+14
* [ARM64_DYNAREC] Cancel native flags when an opcode use native flags not fully...ptitSeb2024-11-171-6/+9
* [ARM64_DYNAREC] Fixed potential issues with 0F A3/AB/B3/BB opcodesptitSeb2024-11-162-8/+13
* [ARM64_DYNAREC] Small optim in emit_sar8c helperptitSeb2024-11-161-2/+1
* [ARM64_DYNAREC] Various fixes and improvments to a few random opcodesptitSeb2024-11-157-68/+141
* [DYNAREC] Zero'd upper 32bits of regs when switching to 32bits from 64bitsptitSeb2024-11-151-5/+18
* [ARM64_DYNAREC] A few fixes to 8/16bits logic/math opcodesptitSeb2024-11-153-16/+16
* [INTERPRETER] Some cleanup on base logic/math/shift operationsptitSeb2024-11-151-6/+0
* [ARM64_DYNAREC] Try to not call UpdateFlags when switching to a DFNONE state ...ptitSeb2024-11-1510-3/+39
* [ARM64_DYNAREC] Very small change on on emit_rol32c helperptitSeb2024-11-151-1/+1
* [RV64_DYNAREC] Added more MMX opcodes for vector (#2037)xctan2024-11-152-0/+119
* [ARM64_DYNAREC] Reworked 8/16/32/64bits TEST opcodesptitSeb2024-11-148-38/+236
* [RV64_DYNAREC] Added more MMX opcodes for vector (#2035)xctan2024-11-141-0/+101
* [DYNAREC] Added a experimental BOX64_DYNAREC_WEAKBARRIER option (#2033)Yang Liu2024-11-142-1/+15
* [ARM64_DYNAREC] Refactor 8/16/32/64bits CMP and REP CMPS/SCAS opcodesptitSeb2024-11-144-51/+115
* [ARM64_DYNAREC] Some refactor on 8/16/32/64bits SHL/SHR/SAR opcodesptitSeb2024-11-143-79/+67
* [ARM64_DYNAREC] Minor change on 16bits neg opcodeptitSeb2024-11-141-2/+0
* [ARM64_DYNAREC] Some rework on 8/16/32/64 INC/DEC opcodesptitSeb2024-11-147-81/+36
* [ARM64_DYNAREC] Small optim for 8/16/32/64bits adc/sbb opcodesptitSeb2024-11-131-32/+22
* [ARM64_DYNAREC] Various small fixes for some 16bits math/logic opcodesptitSeb2024-11-136-36/+35