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authorYang Liu <liuyang22@iscas.ac.cn>2024-11-20 04:22:55 +0800
committerGitHub <noreply@github.com>2024-11-19 21:22:55 +0100
commitfa432bb9d1b4b1069aff1d08681a54e15520f6be (patch)
tree376417b32126731dd4d25a0329a5f03cc3df638a /src/dynarec
parent81e4e26dc51b85720fbc3ba2ffe68030e5d227fa (diff)
downloadbox64-fa432bb9d1b4b1069aff1d08681a54e15520f6be.tar.gz
box64-fa432bb9d1b4b1069aff1d08681a54e15520f6be.zip
[ARM64_DYNAREC] Added weakbarrier=2 to disable last write barriers (#2049)
Diffstat (limited to 'src/dynarec')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_helper.h30
1 files changed, 15 insertions, 15 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_helper.h b/src/dynarec/arm64/dynarec_arm64_helper.h
index 15a2d423..aa06379f 100644
--- a/src/dynarec/arm64/dynarec_arm64_helper.h
+++ b/src/dynarec/arm64/dynarec_arm64_helper.h
@@ -161,21 +161,21 @@
     } while (0)
 
 // An opcode will write memory, this will be put before the STORE instruction automatically.
-#define WILLWRITE()                                                                                   \
-    do {                                                                                              \
-        if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) {           \
-            /* Will write but never written, this is the start of a SEQ, put a barrier. */            \
-            if (box64_dynarec_weakbarrier)                                                            \
-                DMB_ISHST();                                                                          \
-            else                                                                                      \
-                DMB_ISH();                                                                            \
-        } else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && dyn->insts[ninst].last_write) { \
-            /* Last write, put a barrier */                                                           \
-            if (box64_dynarec_weakbarrier)                                                            \
-                DMB_ISHST();                                                                          \
-            else                                                                                      \
-                DMB_ISH();                                                                            \
-        }                                                                                             \
+#define WILLWRITE()                                                                                                                     \
+    do {                                                                                                                                \
+        if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) {                                             \
+            /* Will write but never written, this is the start of a SEQ, put a barrier. */                                              \
+            if (box64_dynarec_weakbarrier)                                                                                              \
+                DMB_ISHST();                                                                                                            \
+            else                                                                                                                        \
+                DMB_ISH();                                                                                                              \
+        } else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && box64_dynarec_weakbarrier <= 1 && dyn->insts[ninst].last_write) { \
+            /* Last write, put a barrier */                                                                                             \
+            if (box64_dynarec_weakbarrier)                                                                                              \
+                DMB_ISHST();                                                                                                            \
+            else                                                                                                                        \
+                DMB_ISH();                                                                                                              \
+        }                                                                                                                               \
     } while (0)
 
 // Similar to WILLWRITE, but checks lock.