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* [DYNAREC_RV64] Fixed A0 MOV AL,Ob (#866)Yang Liu2023-06-262-2/+4
* [32BTIS][DYNAREC_RV64] Added support for 32bits (#861)Yang Liu2023-06-2523-283/+545
* [32BITS][ARM64_DYNAREC] Added 06/07 opcodesptitSeb2023-06-251-1/+19
* [ARM64_DYNAREC] Fixed issue with the newly introduced I64 optim for x87 regs ...ptitSeb2023-06-252-2/+5
* [ARM64_DYNAREC] Fixed 8C opcode and added 66 8C opcodeptitSeb2023-06-252-2/+15
* [ARM64_DYNAREC] Added (F2/F3) 66 A7 opcodeptitSeb2023-06-251-0/+40
* [32BITS][ARM64_DYNAREC] Hanlding of STll struct in FILD/FISTP 64bits (for #870)ptitSeb2023-06-252-0/+46
* [ARM64_DYNAREC] Improved handling of FILD/FISTP i64 sequence, important fo 32...ptitSeb2023-06-256-57/+153
* [32BITS][ARM64_DYNAREC] Added 82 opcodesptitSeb2023-06-251-0/+6
* [32BITS][ARM64_DYNAREC] Added 1E/1F opcodesptitSeb2023-06-251-1/+19
* [32BITS][ARM64_DYNAREC] Added (faked) 6D opcodeptitSeb2023-06-251-0/+28
* [32BITS][ARM64_DYNAREC] Added (faked) EF opcodeptitSeb2023-06-251-0/+9
* [32BITS][ARM64_DYNAREC] Added (F2/F3) 66 AD opcodeptitSeb2023-06-251-0/+23
* [32BITS][ARM64_DYNAREC] Added 64 8F opcodeptitSeb2023-06-252-0/+21
* [DYNAREC] Small improvment on instruction size array memory allocationptitSeb2023-06-253-10/+17
* [32BITS][ARM64_DYNAREC] Added (F2/F3) 66 AF opcodeptitSeb2023-06-251-0/+38
* A few cosmetic fixes (#858)Alexandre Julliard2023-06-2459-91/+3
* [ARM64_DYNAREC] Fix potential issue on FF /5 opcodeptitSeb2023-06-241-3/+3
* [32BITS] Added 66/61 opcodes ([ARM64_DYNAREC] too)ptitSeb2023-06-241-0/+23
* [ARM64_DYNAREC] Fixed a nasty issue with Double Push / Double Pop optimisatio...ptitSeb2023-06-241-14/+18
* [ARM64_DYNAREC] Added 67 66 89 opcodeptitSeb2023-06-241-0/+25
* [ARM64_DYNAREC] Added 67 63 opcodeptitSeb2023-06-241-0/+23
* [ARM64_DYNAREC] Added 67 0F B6/B7 opcodesptitSeb2023-06-241-0/+34
* [32BITS][ARM64_DYNAREC] Added 66 40..4F opcodesptitSeb2023-06-241-0/+31
* [32BITS][ARM64_DYNAREC] Added 66 0F prefixed opcodesptitSeb2023-06-241-5/+0
* [32BITS][ARM64_DYNAREC] Added 66 64 prefixed opcodesptitSeb2023-06-241-5/+0
* [32BITS][ARM64_DYNAREC] Added 66 F0 prefixed opcodesptitSeb2023-06-241-5/+0
* [32BITS][ARM64_DYNAREC] Added 66 prefixed opcodesptitSeb2023-06-241-10/+11
* [32BITS][ARM64_DYNAREC] Added F0 prefixed opcode (except 66 prefix)ptitSeb2023-06-241-5/+0
* [32BITS][ARM64_DYNAREC] Added 64 A1/A3 opcodeptitSeb2023-06-241-0/+24
* [32BITS][ARM64_DYNAREC] Added some dynarec support for 32bits code (no-prefix...ptitSeb2023-06-2414-158/+384
* [32BITS][DYNAREC] Added basic 32 bits RV64 support (#856)Yang Liu2023-06-244-32/+76
* [DYNAREC_RV64] Fixed a typo (#855)Yang Liu2023-06-241-2/+2
* [DYNAREC_RV64] Small optim to FLAGS_ADJUST_TO11 (#854)Yang Liu2023-06-241-6/+6
* [32BITS][DYNAREC] Preparing work for 32bits dynarecptitSeb2023-06-2313-28/+95
* [32BITS][DYNAREC] Preparing Dynarec to handle 32bits codeptitSeb2023-06-224-23/+27
* Added some support for 32bits code (doesn't seems enough for wow64 yet)ptitSeb2023-06-182-18/+32
* Added support for creating 32bits selector (no 32bits execution yet)ptitSeb2023-06-173-5/+22
* Added 0F EA/EE opcodes ([ARM64_DYNAREC] too) (for #829)ptitSeb2023-06-101-2/+14
* [DYNAREC_RV64] Added more opcodes (#828)Yang Liu2023-06-086-4/+136
* [DYNAREC_RV64] Fixed 9x SETcc opcodes (#824)Yang Liu2023-06-063-9/+10
* [DYNAREC] Fixed call_c issues (#823)Yang Liu2023-06-063-19/+22
* [DYNAREC] Fixed native_fprem (#822)Yang Liu2023-06-061-18/+18
* [ARM64_DYNAREC] Fixed PUSH rsp when double pushing (#821)Yang Liu2023-06-051-27/+22
* [RV64_DYNAREC] Small optim on GETGX/GETGM helper macros (#817)Yang Liu2023-06-035-603/+603
* [RV64_DYNAREC] Added more opcodes for ICEY (#816)xctan2023-06-023-0/+100
* [RV64_DYNAREC] Added F0 80 /1 LOCK OR opcode for ICEY (#815)xctan2023-06-011-0/+37
* [RV64_DYNAREC] Fixed 6B IMUL opcode (#812)Yang Liu2023-05-301-3/+3
* [RV64_DYNAREC] Fixed geted32 (#811)Yang Liu2023-05-301-37/+39
* [ARM64_DYNAREC] Fixed OF flag for ror32c emiterptitSeb2023-05-281-1/+1