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* [ARM64_DYNAREC] Optimized 16bits SHL/SHR/SAR opcodesptitSeb2023-11-133-81/+411
* [DYNAREC] Don't consume X_PEND if opcode MAY emit flagsptitSeb2023-11-131-3/+3
* [ARM64_DYNAREC] Added emit_sar8 helperptitSeb2023-11-133-6/+50
* [ARM64_DYNAREC] Add optionnal handling of no flag update for shift CL opcodesptitSeb2023-11-131-0/+22
* [COSIM] Fix GO_TRACE (#1059)Yang Liu2023-11-121-2/+2
* [ARM64_DYNAREC] Some fixes to shift opcodesptitSeb2023-11-121-9/+33
* [ARM64_DYNAREC] More fixes on 8bits shift emitersptitSeb2023-11-122-32/+55
* [ARM64_DYNAREC] Fixed sar8c usageptitSeb2023-11-122-3/+3
* [ARM64_DYNAREC] Some more work on shift opcodesptitSeb2023-11-121-23/+29
* [ARM64_DYNAREC] Added emit_sar8cptitSeb2023-11-113-23/+50
* [ARM64_DYNAREC] Added emit_shr8c and some mare adjustement to 8bits shiftsptitSeb2023-11-113-44/+72
* [ARM64_DYNAREC] Added emit_shr8 helperptitSeb2023-11-113-14/+55
* [ARM64_DYNAREC] improved D2 /4/6 opcodesptitSeb2023-11-113-7/+58
* [ARM64_DYNAREC] Fixed 64/65 8E opcodeptitSeb2023-11-111-0/+1
* [ARM64_DYNAREC] Reorganised D0/D2 opcodes and Added shl8c emitter useptitSeb2023-11-111-96/+132
* [ARM64_DYNAREC] Added shl8c emitterptitSeb2023-11-113-13/+57
* [ARM64_DYNAREC] Fixed OF flags for 8 bit addition when using FLAGM extensionptitSeb2023-11-111-3/+3
* [ARM64_DYNAREC] More fixing and improving on shifting opcodesptitSeb2023-11-1011-126/+391
* [ARM64_DYNAREC] Added 64/65 8E opcodeptitSeb2023-11-101-1/+15
* [RV64_DYNAREC] Fixed a nasty typo in add8c emitterptitSeb2023-11-091-1/+1
* [ARM64_DYNAREC] More accurate 0F BA opcodes on 64bits without rex.wptitSeb2023-11-091-5/+1
* [ARM64_DYNAREC] Fixed 66 0F 3A 21 opcodeptitSeb2023-11-061-51/+4
* [ARM64_DYNAREC] Added F0 0F BA opcodesptitSeb2023-11-061-4/+139
* [ARM64_DYNAREC] Added 66 0F 3A 40 opcode (with tests)ptitSeb2023-11-063-0/+42
* [RV64_DYNAREC] Fix test faillingptitSeb2023-11-041-27/+0
* [ARM64_DYNAREC] Added 66 0F F2 38 F1 opcodeptitSeb2023-11-041-0/+29
* Added 66 0F F2 38 F1 opcode, and fixed all 66 0F F2/F3 xx opcodes (should hel...ptitSeb2023-11-049-5/+265
* [ARM64_DYNAREC] Added 66 0F 3A 60..63 opcodesptitSeb2023-10-305-4/+208
* [ARM64_DYNAREC] Added support for F2 0F 38 F0/F1 CRC32 opcodesptitSeb2023-10-302-21/+39
* [ARM64_DYNAREC] Better fix for x87 i64 promotion to DoubleptitSeb2023-10-273-7/+9
* [ARM64_DYNAREC] Fixed and improved i64 x87 optimisationptitSeb2023-10-274-24/+38
* [ARM64_DYNAREC] Ported fprem/fprem1 from box86 (fix camera issues in FlatOut ...ptitSeb2023-10-271-0/+46
* [ARM64_DYNAREC] Small optim on Load/Unload x87 cacheptitSeb2023-10-271-6/+10
* [ARM64_DYNAREC] Added LDR/STR SIMD printerptitSeb2023-10-271-1/+24
* [WRAPPER] Fixed my_execl (#1044)wannacu2023-10-271-11/+75
* [32BITS] Added a few 66 opcodes ([ARM64_DYNAREC] too)ptitSeb2023-10-261-1/+17
* [ARM64_DYNAREC] Fixes STUR print opcodeptitSeb2023-10-261-5/+5
* [DYNAREC_RV64] Fixed x87 FCOMI opcodes (#1041)Yang Liu2023-10-262-2/+2
* [DYNAREC_RV64] Fixed opcode FLD tbyte (for #871) (#1040)Yang Liu2023-10-261-1/+1
* [ARM64_DYNAREC] Small optimisation on 66 0F 57 opcodeptitSeb2023-10-251-3/+10
* [DYNAREC] Various improvment to x87 code and segment handlingptitSeb2023-10-259-14/+93
* [32BITS] Added 66 06/07 and 66 1E/1F opcodes ([ARM64_DYNAREC] too)ptitSeb2023-10-241-0/+38
* [ARM64_DYNAREC] Fixed some cases of 0F D3 opcodeptitSeb2023-10-232-6/+8
* [RV64_DYNAREC] Fixed an issue with MMX Cache transformationptitSeb2023-10-231-1/+1
* [ARM64_DYNAREC] Fixed an issue with MMX Cache transformationptitSeb2023-10-231-1/+1
* [ARM64_DYNAREC][32BITS] Added 67 64 A3 opcodeptitSeb2023-10-231-1/+15
* [ARM64_DYNAREC][32BITS] Added 67 64 FF /6 opcodeptitSeb2023-10-235-1/+176
* [ARM64_DYNAREC] Some fixes to x87 opcodes (helps 32bits games on WoW64)ptitSeb2023-10-232-8/+25
* [ARM64_DYNAREC] Fixed 0F F4 opcode (for #1036)ptitSeb2023-10-221-3/+3
* [ARM64_DYNAREC] Fixed an issue with refect_cache_mmx helper functionptitSeb2023-10-221-1/+1