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* [ARM64_DYNAREC] Added AVX.0F 58-59 opcodes, and fixed AVX.66.0F3A 18 opcodeptitSeb2024-05-303-4/+24
* [ARM64_DYNAREC] Added AVX.66.0F38 18 and AVX.66.0F3A 0C opcodesptitSeb2024-05-305-0/+150
* [ARM64_DYNAREC] Added AVX.0F 57 opcodeptitSeb2024-05-302-0/+37
* [ARM64_DYNAREC] Added AVX.66.0F3A 18 opcodeptitSeb2024-05-304-1/+98
* [ARM64_DYNAREC] That first avx opcode now is 256bits enabledptitSeb2024-05-3026-313/+582
* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1539)xctan2024-05-303-60/+306
* [ARM64_DYNAREC] Added a fisrt 128bits only AVX opcodeptitSeb2024-05-3018-19/+359
* Added more MMX opcodes and some optimizations too (#1537)xctan2024-05-302-22/+110
* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1535)xctan2024-05-284-21/+187
* [ARM64_DYNAREC] Added faked 0F C7 /4 opcode to get bigger dynablockptitSeb2024-05-271-1/+6
* [ARM64_DYNAREC] Fixed some SHA1 opcode when source is same as destptitSeb2024-05-271-5/+6
* [ARM64_DYNAREC] Some fixes to opcode when src is same as destptitSeb2024-05-271-2/+8
* [ARM64_DYNAREC] Fixed some pcmp[ei]stri flagsptitSeb2024-05-271-7/+8
* Added 67 66 83 opcodes ([ARM64_DYNAREC] too)ptitSeb2024-05-262-0/+96
* Added 67 66 0F D6 ([ARM64_dynarec] too)ptitSeb2024-05-251-0/+23
* [RV64_DYNAREC] Fix dynarec build for RV64ptitSeb2024-05-242-4/+4
* more avx infrastructureptitSeb2024-05-241-1/+1
* Added support for XSAVE/XRSTOR ([ARM64_DYNAREC] too)ptitSeb2024-05-243-11/+33
* [LA64_DYNAREC] Added more opcodes (#1528)Yang Liu2024-05-2310-8/+498
* [ARM64_DYNAREC] Added 66 D9 /6 and 66 DD /4 /6 opcodesptitSeb2024-05-233-2/+76
* [LA64_DYNAREC] Added CMPXCHG8B and CMPXCHG16B opcodes (#1527)Yang Liu2024-05-234-0/+117
* [RV64_DYNAREC] Fixed LOCK XCHG byte opcode (#1526)Yang Liu2024-05-231-4/+34
* [LA64_DYNAREC] Added more opcodes (#1525)Yang Liu2024-05-233-0/+157
* [ARM64_DYNAREC] Small potential fix to D9 E5 opcodeptitSeb2024-05-221-0/+6
* [LA64_DYNAREC] Fixed more issues here and there (#1521)Yang Liu2024-05-225-10/+30
* [LA64_DYNAREC] Fixed some non-lbt flags comutation issues (#1520)Yang Liu2024-05-223-10/+17
* [LA64_DYNAREC] Fixed LOCK XCHG byte opcode fallback path (#1519)Yang Liu2024-05-221-4/+34
* [DYNAREC] Simplified emit_pf helper (#1518)Yang Liu2024-05-223-27/+27
* [ARM64_DYANREC] Simplified emit_pf helperptitSeb2024-05-226-93/+90
* [ARM64_DYNAREC] Some small fixes to D9 E5 opcodeptitSeb2024-05-211-13/+9
* [RV64_DYNAREC] Fixed a bunch of x87 opcodesptitSeb2024-05-215-46/+179
* [RV64_DYNAREC] Fixed some MMX opcodes (#1513)Yang Liu2024-05-211-2/+6
* [ARM64_DYNAREC] Fixed PSLLD/PSLLQ opcodes (#1512)Yang Liu2024-05-212-5/+11
* [RV64_DYNAREC] Fixed a few more opcodesptitSeb2024-05-203-6/+7
* [RV64_DYNAREC] Fixed some bit manipulation opcodesptitSeb2024-05-202-2/+20
* [RV64_DYNAREC] Fixed some issue with shld/shrd emitterptitSeb2024-05-202-25/+29
* [RV64_DYNAREC] Fixed some rotation emitersptitSeb2024-05-203-26/+38
* [RV64_DYNAREC] Fixed some math emiter issuesptitSeb2024-05-203-12/+16
* [LA64_DYNAREC] Fixed 66 0F 67 PACKUSWB opcode (#1508)Yang Liu2024-05-201-0/+5
* [LA64_DYNAREC] Fixed LOCK ADD opcode (#1507)Yang Liu2024-05-201-3/+5
* [ARM64_DYNAREC] Some various fixes after double-check of codeptitSeb2024-05-191-2/+3
* [ARM64_DYNAREC] Use optimized rcl/rcr emiter for remaining opcodes with 64/65...ptitSeb2024-05-192-28/+16
* [ARM64_DYNAREC] Small optimisation for edge case on a few shift emiterptitSeb2024-05-181-4/+14
* [ARM64_DYNAREC] Improved stability of RCL/RCR and added 32/64 bits with const...ptitSeb2024-05-174-66/+122
* [ARM64_DYNAREC] Minor adjustments to a few complex x87 opcodesptitSeb2024-05-173-5/+10
* [ARM64_DYNAREC] Small improvment to DD /1 opcodeptitSeb2024-05-151-3/+2
* [ARM64_DYNAREC] Added 64/65 13 opcodeptitSeb2024-05-151-0/+11
* [ARM64_DYNAREC] Fixed a potential issue with 0F B1 opcodeptitSeb2024-05-151-1/+7
* [DYNAREC] Small fixes to when to stop a block (fixes regression on EALauncher)ptitSeb2024-05-151-9/+8
* [ARM64_DYNAREC] Small optim of 0F B1 opcodeptitSeb2024-05-151-29/+25