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* [DYNAREC] Fixed alternate address testing when retriving dynablock (#2638)Yang Liu2025-05-152-4/+3
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* [RV64_DYNAREC] Added more opcodes for vector (#2637)Yang Liu2025-05-152-1/+30
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* [DYNAREC] More minor changes to missing VEX prefixed opcodes (#2636)Yang Liu2025-05-152-2/+3
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* [ARM64_DYNAREC][TRACE] Yet another small change on DYNAREC_MISSING=1 ↵ptitSeb2025-05-151-1/+1
| | | | handling of missing VEX prefixed opcodes
* [ARM64_DYNAREC][TRACE] Anothor small change on DYNAREC_MISSING=1 handling of ↵ptitSeb2025-05-151-1/+1
| | | | missing VEX prefixed opcodes
* [ARM64_DYNAREC][TRACE] Improved DYNAREC_MISSING=1 handling of missing VEX ↵ptitSeb2025-05-151-2/+2
| | | | prefixed opcodes
* [RV64_DYNAREC] Added and optimized some SSE/MMX opcodes (#2635)Yang Liu2025-05-152-45/+60
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* [RV64_DYNAREC] Fixed a typo introduced lately (#2634)Yang Liu2025-05-141-1/+1
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* [RV64_DYNAREC] Added more mmx opcodes (#2629)Yang Liu2025-05-142-9/+68
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* [RV64_DYNAREC] Added more mmx opcodes (#2630)Yang Liu2025-05-131-1/+41
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* [RV64_DYNAREC] Added more mmx opcodes (#2627)Yang Liu2025-05-131-3/+39
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* [RV64_DYNAREC] Added more mmx opcodesYang Liu2025-05-132-1/+112
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* [ARM64_DYNAREC] Fixed a regression introduced with ↵ptitSeb2025-05-101-0/+3
| | | | e7b71cba5fe8ef92cc50266ed380203b7b2ed4ef (fixed broken rendering with American Truck Simulator linux version, probably others too)
* [GDBJIT] Added a new option to register debuginfo only after trapped into ↵Yang Liu2025-05-092-1/+8
| | | | signalhandler (#2614)
* [DYNAREC] Use PE volatile metadata in dynarec (#2610)Yang Liu2025-05-0714-84/+132
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* [ARM64_DYNAREC] Fixed a regression on 256bits VBROADCAST[B/W] opcodesptitSeb2025-05-031-2/+2
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* [ARM64_DYNAREC] Fixed generic case of VPSHUFD opcode on memoryptitSeb2025-05-031-1/+1
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* [ARM64_DYNAREC] Better log for scratch after ymm warningptitSeb2025-05-031-2/+10
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* [ARM64_DYNAREC] Fixed an issue introduced with fastnan=0 handling of SQRTSS ↵ptitSeb2025-05-021-2/+2
| | | | (for #2593)
* [ARM64_DYNAREC] Small changes in a few AVX shift opcodesptitSeb2025-05-011-21/+6
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* [ARM64_DYNAREC] Added missing instruction nameptitSeb2025-05-011-2/+2
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* [ARM64_DYNAREC] Fixed edge-case for VPERM2[F/I]128 opcodesptitSeb2025-05-011-2/+2
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* [ARM_DYNAREC] Small improvments to VMASKMOVP[S/D] opcodesptitSeb2025-05-011-100/+63
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* [ARM64_DYNAREC] Cosmetic change to VGATHER[D/Q]P[D/S] opcodesptitSeb2025-04-301-2/+4
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* [ARM64_DYNAREC] Small rework on VFMAD*S[S/D] opcodesptitSeb2025-04-301-3/+6
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* [ARM64_DYNAREC] Small improvment to VPBROADCAST[B/W] opcodesptitSeb2025-04-301-20/+10
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* [ARM64_DYNAREC] Fixed a potential issue with (V)STMXCSR opcodesptitSeb2025-04-302-2/+2
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* [ARM64_DYNAREC] Add fastnan=0 handling in (V)SQRTSS opcodesptitSeb2025-04-303-3/+27
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* [ARM64_DYNAREC] Switched RSQRTPS to precise instead of aproximateptitSeb2025-04-291-1/+8
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* [ARM64_DYNAREC] Switched RPCPS opcode to precise 1/A instead of approximateptitSeb2025-04-291-1/+7
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* [ARM64_DYNAREC] Small optim on PTEST opcodeptitSeb2025-04-291-17/+21
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* [RV64_DYNAREC] Minor optim to 8 bit TEST opcode (#2583)Yang Liu2025-04-283-13/+18
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* [RV64_DYNAREC] Small optimization to LEA opcode (#2582)Yang Liu2025-04-283-8/+9
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* [ARM64_DYNAREC] Mostly cosmetic changes to SSE/AVX packed shift opcodesptitSeb2025-04-282-43/+37
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* [RV64_DYNAREC] Optimized rv64 printer for pseudo and jump instructions (#2581)Yang Liu2025-04-281-7/+55
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* [RV64_DYNAREC] Minor adjustment to dynarec_missing=2 (#2578)Yang Liu2025-04-283-4/+4
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* [ARM64_DYNAREC] Small optim for PSIGN[B/W/D] opcodesptitSeb2025-04-272-33/+27
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* [ARM64_DYNAREC] Some work on UD flags on (66) F3 0F BC/BD opcodesptitSeb2025-04-272-16/+64
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* [ARM64_DYNAREC] More work on UD flags for (66) F3 0F BC/BD opcodesptitSeb2025-04-272-4/+60
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* [ARM64_DYNAREC] Minor fox to F6 /7 opcodeptitSeb2025-04-271-1/+1
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* [ARM64_DYNAREC] Refactored (V)PSHUFD opcodesptitSeb2025-04-262-111/+183
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* [ARM64_DYNAREC] Allow shift with saturation on (V)PMULH(U)W because it will ↵ptitSeb2025-04-263-10/+5
| | | | never saturate
* [ARM64_DYNAREC] Small fix for edge cases on (V)PMULHUW opcodesptitSeb2025-04-263-8/+10
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* [ARM64_DYNAREC] Fixed (rarely used) some edge case for (V)PMULHRSW opcode ↵ptitSeb2025-04-255-4/+67
| | | | (and improved tests)
* [ARM64_DYNAREC] Small optim on some 256bits VPMOV[S/Z]X* opcodesptitSeb2025-04-251-22/+14
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* [ARM64_DYNAREC] Allow bigger block to be builtptitSeb2025-04-252-3/+5
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* [ARM64_DYNAREC] Minor change, (V)PMOVMSKB is only valid on register, not memoryptitSeb2025-04-252-39/+47
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* [ARM64_DYNAREC] Fixed a potential issue with PCMPEQQ opcodes, and many ↵ptitSeb2025-04-251-63/+63
| | | | missing space in instruction name
* [ARM64_DYNAREC] Improved and fixed software fallback for (V)PCLMULQDQ opcodesptitSeb2025-04-242-37/+24
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* [ARM64_DYNAREC] Some optimisation to some (V)(P)BLEND* opcodesptitSeb2025-04-242-63/+21
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