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* [RV64_DYNAREC] Fixed x87 cache swapping (#2571)Yang Liu2025-04-242-9/+11
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* [ARM64_DYNAREC] Small optim on (V)PACKUSDW opcodesptitSeb2025-04-242-14/+4
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* [LA64_DYNAREC] Add/Opt more mmx/sse ops (#2565)phorcys2025-04-242-46/+180
| | | | | | | | | | | | | | | * [LA64_DYNAREC] Add/Opt PEXTR{B,W,D,Q}/PINSR{B,W,D,Q} . * 0f.c4/c5 PINSRW/PEXTRW mmx ops. * 66.0f.3a.14/15/16 PEXTR{B,W,D/Q} SSE4 ops. * 66.0f.c4/c5 PINSRW/PEXTRW sse ops. * [LA64_DYNAREC] Add more SSE3/SSE4 ops 66.0f.38.28 PMULDQ 66.0f.38.2a MOVNTDQA 66.0f.38.37 PCMPGTQ 66.0f.38.38/3b/3c/3f PMINSB/PMINUD/PMAXSB/PMAXUD 66.0f.3a.17 EXTRACTPS 66.0f.3a.41 DPPD opt 66.0f.3a.40 DPPS
* [ARM64_DYNAREC] Simplified code for MOVS[H/L]DUP opcodesptitSeb2025-04-242-19/+3
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* [LA64_DYNAREC] Add POPCNT/TZCNT/LZCNT ops. (#2566)phorcys2025-04-245-8/+170
| | | | | 66.f3.0f.b8/bc/bd POPCNT/TZCNT/LZCNT 16bits ops f3.0f.bd LZCNT fix f3.0f.bc TZCNT (GETED/RESTORE_EFLAGS x1 conflict)
* [ARM64_DYNAREC] Small iùprovments to some (V)MOVQ opcodesptitSeb2025-04-244-11/+12
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* [ARM64_DYNAREC] Small change and optims to various (V)MOVNT* opcodesptitSeb2025-04-244-33/+24
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* [DYNAREC] Added ranged Dynablock dump (#2570)Yang Liu2025-04-2421-90/+96
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* [ARM64_DYNAREC] Minor optim to MOVNTDQA (#2568)Yang Liu2025-04-241-3/+10
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* [ARM64_DYNAREC] Small fixes and improvments to (V)MOVMSKP[S/D] opcodesptitSeb2025-04-234-15/+12
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* [ARM64_DYNAREC] Few fixes and small cosmetic changes to some partial (V)MOV ↵ptitSeb2025-04-238-58/+36
| | | | opcodes
* [ARM64_DYNAREC] Made REP MOVSB optimisation flaglessptitSeb2025-04-231-4/+4
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* [ARM64_DYNAREC] Optimized REP STOSBptitSeb2025-04-232-2/+36
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* [ARM64_DYNAREC] Various improvment to various SSE/AVX 128bits/256bits mov ↵ptitSeb2025-04-238-89/+144
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* [DYNAREC] Added a x87pc test and some cosmetic changes too (#2561)Yang Liu2025-04-2216-158/+83
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* [LA64_DYNAREC] Add SSSE3's mmx ops. (#2559)phorcys2025-04-221-0/+162
| | | | | | | | | | | | | | | | | 0f.38.00 PSHUFB 01 PHADDW 02 PHADDD 03 PHADDSW 04 PMADDUBSW 05 PHSUBW 06 PHSUBD 07 PHSUBSW 08 PSIGNB 09 PSIGNW 0a PSIGND 0b PMULHRSW 1c PABSB 1d PABSW 1e PABSD
* [ARM64_DYNAREC] Improved (V)[MIN/MAX][S/P][S/D] opcodesptitSeb2025-04-224-34/+10
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* [RV64_DYNAREC] Better handling of x87double=2 (#2560)Yang Liu2025-04-2210-1/+47
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* [ARM64_DYNAREC] Small improvements to (V)MASKMOVDQU opcodeptitSeb2025-04-212-6/+4
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* [ARM64_DYNAREC] Better handling of x87double=2ptitSeb2025-04-2110-0/+53
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* [ARM64_DYNAREC] Fixed potential issue with (V)LDDQU opcodeptitSeb2025-04-212-3/+3
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* [DYNAREC] More handling of low precision x87 flag change (#2556)Yang Liu2025-04-214-2/+8
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* [RV64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and ↵Yang Liu2025-04-211-1/+1
| | | | cosim scenario (#2555)
* [ARM64_DYNAREC] Add/Improved (V)H[ADD/SUB]P[S/D] opcodesptitSeb2025-04-216-23/+53
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* [ARM64_DYNAREC] Small change to 66 0F 3A 17 opcodeptitSeb2025-04-211-2/+2
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* [ARM64_DYNAREC] Minor cosmetic changesptitSeb2025-04-212-2/+2
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* [RV64_DYNAREC] Added X87DOUBLE=2 support (#2553)Yang Liu2025-04-2122-24/+88
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* [ARM64_DYNAREC] Another potential fix for X87DOUBLE=2ptitSeb2025-04-211-1/+1
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* [ARM64_DYNAREC] Fixed some potential issues with BOX64_DYNAREC_DOUBLE=2ptitSeb2025-04-213-4/+1
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* [DYNAREC][TRACE] Slightly better trace message on creating dynablockptitSeb2025-04-181-2/+2
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* [LA64_DYNAREC]Add/opt more SSE/MMX ops (#2543)phorcys2025-04-182-24/+60
| | | | | | | | | | * Add SSE2 op MASKMOVDQU. * Opt PSADBW. * Add SSE3 HSUBPD op. * Add mmx PALIGNR op. * Fix PSRLDQ. * Fix PSRAW Gx,Ex PSRAW Gm,Em. mmx/sse get COUNT from Em/Ex as an 64bit unsigned... testsuite with shift 0x4,0x4,0x4,0x4, result COUNT as 0x04040404.
* [DYNAREC] Small improvment to callret=2 handling of path to regen a blockptitSeb2025-04-181-0/+2
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* [WOW64] Finished skeleton code for PE build (#2542)Yang Liu2025-04-172-2/+0
| | | | | * [WOW64] Finished skeleton code for PE build * move musl to external
* [LA64_DYNAREC] Add SSE1/SSE2's cvt mmx ops. (#2538)phorcys2025-04-172-0/+166
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* [ARM64_DYNAREC] More handling of low precision x87 flag changeptitSeb2025-04-163-0/+4
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* [DYNAREC] Introduce BOX64_DYNAREC_X87DOUBLE=2 to handle Low Precision x87 ↵ptitSeb2025-04-1617-21/+114
| | | | ([ARM64_DYNAREC] only for now)
* [LA64_DYNAREC] Add mmx pack/unpack ops. (#2536)phorcys2025-04-161-9/+83
| | | | | add PUNPCKL{BW,WD,DQ}, PUNPCKH{BW,WD,DQ} mmx ops. add PACKSSWB PACKUSWB PACKSSDW mmx ops. * fix some merge mistake in prev mmx commit.
* [ARM64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and ↵ptitSeb2025-04-151-1/+1
| | | | cosim scenario
* [ARM64_DYNAREC][TRACE] Changed TBZ/TBNZ printer to print bit offset in decimalptitSeb2025-04-151-2/+2
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* [ARM64_DYNAREC] Added 67 0F 29 opcodeptitSeb2025-04-152-0/+41
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* [DYNAREC] Fix on strongmem mode were last write on a seq on 1 write could be ↵ptitSeb2025-04-151-1/+4
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* [LA64_DYNAREC] Add mmx cmp ops. (#2533)phorcys2025-04-151-0/+41
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* [RV64_DYNAREC] fix MASKMOVQ. (#2531)phorcys2025-04-141-1/+1
| | | | | maskmovq write when sign bit == 1. if mask byte = 0x00, should skip. replace BLT with BLE.
* [LA64_DYNAREC] Add mmx arith ops. (#2530)phorcys2025-04-141-0/+71
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* [LA64_DYNAREC] Add mmx shift ops. (#2529)phorcys2025-04-141-0/+148
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* [WOW64] More tweaks for PE build (#2528)Yang Liu2025-04-1410-22/+71
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* [LA64_DYNAREC] Optimize sse_setround (#2527)phorcys2025-04-141-10/+3
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* [LA64_DYNAREC] Add mmx related mov op (#2526)phorcys2025-04-144-15/+102
| | | | | * [LA64_DYNAREC] Add SSE2's MOVQ2DQ/MOVDQ2Q mmx op * [LA64_DYNAREC] Add mmx mov ops.
* [LA64_DYNAREC] Update la64 mmx infra. (#2524)phorcys2025-04-124-55/+846
| | | Co-authored-by: phorcys <phorcys02@126.com>
* [WOW64] Splitted freq and cleanup functions from x64emu (#2521)Yang Liu2025-04-113-4/+4
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