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* [ARM64_DYNAREC] Some more FRINTTS and AVX/SSE fixes (might help #2520)ptitSeb2025-04-115-30/+22
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* [DYNAREC] Speedup a bit DYNAREC_DIRTY=1ptitSeb2025-04-102-13/+24
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* [WOW64] More tweaks towards PE build (#2519)Yang Liu2025-04-106-13/+13
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* [WOW64] More work on the PE wow64 build (#2518)Yang Liu2025-04-106-12/+10
| | | | | * [WOW64] More work on the PE wow64 build * added a TODO
* [DYNAREC] Improved handling of db_size rbtreeptitSeb2025-04-091-16/+7
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* [DYNAREC] Better handling of self-loop and added CALLRET=2 settings (ARM64 ↵ptitSeb2025-04-0915-19/+151
| | | | only, RV64 and LA64 todo)
* Moved emit functions to seperate files from signals.h (#2516)Yang Liu2025-04-091-0/+1
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* [ARM64_DYNAREC] Fixed some dangling else warnings (#2514)Yang Liu2025-04-091-6/+18
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* [WOW64] Add wow64 PE build scaffolding (#2513)Yang Liu2025-04-081-2/+0
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* [DYNAREC] Do not mark a dynablock as always_test for loop on itself that are ↵ptitSeb2025-04-081-6/+10
| | | | not alive
* [ARM4_DYNAREC] A few changes to seem SSE/AVX comparison and convertions ↵ptitSeb2025-04-048-154/+287
| | | | opcodes, and more FRINTTS usage too
* [ARM64_DYNAREC] Small adjustement to 2 AVX opcodesptitSeb2025-04-041-3/+3
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* [LA64_DYNAREC] Optimize la64 MAXPD/MAXPS. (#2499)phorcys2025-04-032-8/+4
| | | Co-authored-by: phorcys <phorcys02@126.com>
* Decoupled alternate functions from bridge (#2500)Yang Liu2025-04-035-1/+5
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* Moved more functions to os.h (#2497)Yang Liu2025-04-0397-119/+23
| | | | | | | * Removed some unused function declarations * Moved more functions to os.h * review
* [ARM64_DYNAREC] Removed some condition on vex.l that shouldn't be here on a ↵ptitSeb2025-04-032-6/+6
| | | | few AVX opcodes
* [LA64_DYNAREC] Add more sse ops (#2493)phorcys2025-04-034-32/+283
| | | | | | | | | | | fix 0F.5D/5F MINPS/MAXPS fix unordered. fix 66.0F.5D/5F MINPD/MAXPD fix unordered. 66.0F.3A.08/09/0A ROUNDPS/ROUNDPD/ROUNDSS 66.0F.3A.0C/0D BLENDPS/BLENDPD 66.0F.3A.21 INSERTPS 66.0F.C2 CMPPD printer add VFCMP.cond.s/d, vbitsel.v: Co-authored-by: phorcys <phorcys02@126.com>
* [ARM64_DYNAREC] Small optim for VBLENDPS opcodeptitSeb2025-04-021-6/+14
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* [ARM64_DYNAREC] Fixed an optim in BLENDPS opcodeptitSeb2025-04-021-2/+2
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* Moved some emit functions to os.h (#2494)Yang Liu2025-04-022-12/+7
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* Moved more OS-dependent functions to os.h (#2491)Yang Liu2025-04-012-18/+7
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* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-01109-215/+109
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* [LA64_DYNAREC] Fix f0.80.1 LOCK OR, LoongArch ANDI is zero-extended. (#2489)phorcys2025-04-011-1/+2
| | | Co-authored-by: phorcys <phorcys02@126.com>
* Added os.h for future usage (#2488)Yang Liu2025-04-013-0/+3
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* Some cosmetic changes to C header files (#2487)Yang Liu2025-04-017-35/+5
| | | | | * [DYNAREC] Move cosim functions to a new header * Moved isNativeCall to elfloader
* [ARM64] Use crc32 hardware support (if available) for dynablock signatureptitSeb2025-03-313-0/+28
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* [ARM64_DYNAREC] Added atomic support for various lock helpersptitSeb2025-03-302-0/+129
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* [RV64] Improved rv64_lock_cas[b/h] helpersptitSeb2025-03-301-2/+2
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* [LA64] Fixed la64_lock_cas_[h/b]_slow helper (rarely used)ptitSeb2025-03-301-2/+2
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* [ARM64_DYNAREC] Fixed a potential issue with SSE regs when internal jumping ↵ptitSeb2025-03-292-3/+24
| | | | to a native call
* [LA64_DYNAREC] Added more MMX opcodes (#2479)Yang Liu2025-03-281-70/+233
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* [LA64_DYNAREC] Added more MMX opcodes (#2477)Yang Liu2025-03-284-0/+125
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* [LA64_DYNAREC] Added preliminary MMX support (#2476)Yang Liu2025-03-286-45/+200
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* [LA64_DYNAREC] Added more opcodes (#2475)Yang Liu2025-03-281-26/+76
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* [LA64_DYNAREC] Added more opcodes (#2473)Yang Liu2025-03-271-0/+71
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* [LA64_DYNAREC] Added more opcodes (#2472)Yang Liu2025-03-271-0/+30
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* [ARM64_DYNAREC] Added fastnan=0 path for HSUBPS opcodeptitSeb2025-03-261-0/+13
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* [ARM64_DYNAREC] Improved VHSUBPS opcode, and added fastnan=0 pathptitSeb2025-03-261-13/+16
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* [ARM64_DYNAREC] Commented a message that doesn't seems releventptitSeb2025-03-261-2/+2
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* [COSIM] Changed how F0 LOCK opcodes are skipped in COSIMptitSeb2025-03-261-1/+1
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* [ARM64_DYNAREC] Improved (V)HADDPS with fastnan=0ptitSeb2025-03-262-4/+39
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* [ARM64_DYNAREC] Addedfastnan=0 code to (V)SQRTPS opcodesptitSeb2025-03-262-4/+30
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* [ARM64_DYNAREC] Improved (V)MAXP[S/D] and (V)MINP[S/D] opcodes to more ↵ptitSeb2025-03-264-40/+47
| | | | closely match x6 behavior when using fastnan=0 (for #1046)
* [ARM64_DYNAREC] Small change on AVX.66.0F38 BA opcode to more closely match ↵ptitSeb2025-03-261-3/+11
| | | | x86 behavior (for #1046)
* [RV64_DYNAREC] Fixed 66 0F 6A PUNPCKHDQ opcodes (#2468)Yang Liu2025-03-261-2/+2
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* [RV64_DYNAREC] Minor improvement to DD /7 FNSTSW opcode (#2467)Yang Liu2025-03-251-0/+1
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* [RV64_DYNAREC] Fixed D9 E5 FXAM opcode (#2466)Yang Liu2025-03-251-3/+3
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* [RV64_DYNAREC] Small optim to vsetvli usage (#2465)Yang Liu2025-03-251-1/+3
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* [RV64_DYNAREC] Fixed scratch conflicts with fastround=0 in some x87 opcodes ↵Yang Liu2025-03-245-14/+11
| | | | | | | | | (#2464) * [RV64_DYNAREC] Fixed scratch conflicts with fastround=0 in some x87 opcodes * another fix * more fix
* [RV64_DYNAREC] Fixed some DD prefixed x87 opcodes (#2463)Yang Liu2025-03-241-2/+10
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