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* [DYNAREC] Better handling of blocksize limit when generating very large ↵ptitSeb2025-03-243-13/+27
| | | | dynablocks
* [ARM64_DYNAREC] Better log for arch_populate buffer being undersizedptitSeb2025-03-221-3/+2
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* [ARM64_DYNAREC] Fixed potential issue on unligned path being marked while ↵ptitSeb2025-03-222-4/+4
| | | | dynablock is building
* [ARM64_DYNAREC][TRACE] Added a message on Dump for Unaligned path on opcodesptitSeb2025-03-225-0/+7
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* [ARM64_DYNAREC] Added 67 66 0F 76/EF opcodes (for #1046)ptitSeb2025-03-211-1/+36
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* [RV64_DYNAREC] Fixed many minor issues (#2451)Yang Liu2025-03-196-60/+65
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* [DYNAREC] Fixed minor issues for F0 0F B0/B1 LOCK CMPXCHG opcodes (#2448)Yang Liu2025-03-193-24/+20
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* [RV64_DYNAREC] Added 66 F0 0F B1 LOCK CMPXCHG opcode (#2447)Yang Liu2025-03-181-0/+53
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* [RV64_DYNAREC] More minor changes and fixes to x87 opcodes (#2443)Yang Liu2025-03-175-91/+63
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* [DYNAREC] Small change in strongmem to end a SEQ with a Brrier at last_write ↵ptitSeb2025-03-171-2/+3
| | | | directly
* [DYNAREC] Change in strongmem managment to end a SEQ on jump arrival and not ↵ptitSeb2025-03-171-1/+1
| | | | forget the SEQ
* [ARM64_DYNAREC] Small optim on special case of LOCK OR [RSP], 0ptitSeb2025-03-171-15/+19
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* [ARM64_DYNAREC] Simplified 8F opcode, so special cases will be handled in ↵ptitSeb2025-03-171-9/+3
| | | | signal directly if needed
* [ARM64_DYNAREC] Added missing SMWRITE2 to another AVX opcodeptitSeb2025-03-171-0/+1
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* [ARM64_DYNAREC] Added some missing SMWRITE2 for strongmem=2 on a few AVX opcodesptitSeb2025-03-173-0/+9
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* [ARM64_DYNAREC] Added printer for RET opcodesptitSeb2025-03-171-0/+7
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* [RV64_DYNAREC] Minor D8..DF opcodes refactor (#2442)Yang Liu2025-03-178-1703/+1552
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* [RV64_DYNAREC] Minor x87 changes to enable test31 (#2441)Yang Liu2025-03-173-23/+21
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* [RV64_DYNAREC] Fixed some x87 rounding cases for fastround=0 (#2437)Yang Liu2025-03-137-19/+114
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* [DYNAREC] Introduced DYNAREC_DIRTY=2 and changed a profile to use itptitSeb2025-03-121-1/+4
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* [TRACE] Small work on traceptitSeb2025-03-111-4/+5
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* [RV64_DYNAREC] Added 66 F0 81/83 /4 opcodeptitSeb2025-03-101-0/+66
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* [RV64_DYNAREC] Reduce the number of false-positive for dynarec missing opcodeptitSeb2025-03-101-17/+18
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* [RV64_DYNAREC] Added 66 F0 81/83 /1 opcodeptitSeb2025-03-101-0/+66
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* [RV64_DYNAREC] Small change in F0 0F C7 opcodeptitSeb2025-03-101-1/+1
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* [DYNAREC] Don't continue a dynablock if entering an hotpageptitSeb2025-03-101-1/+1
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* [RV64_DYNAREC] Optimized PMOVZX and PMOVSX opcodes for vector 1.0 (#2430)Yang Liu2025-03-101-124/+269
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* [LA64_DYNAREC] This should fix the buildptitSeb2025-03-091-1/+1
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* [ARM64_DYNAREC] Improced arch_build helpers function to only compute build ↵ptitSeb2025-03-086-36/+53
| | | | steps 1 time per dynablock
* [ARM64_DYNAREC] Removed obsolete commentptitSeb2025-03-081-1/+0
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* [ARM64_DYNAREC] Fixed a potential issue with AVX.0F 50 opcodeptitSeb2025-03-081-1/+1
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* [ARM64_DYNAREC] Fixed a few potential issue with some AVX opcodesptitSeb2025-03-084-20/+20
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* [ARM64_DYNAREC] Fixed inlined ClearCache, re-enabling itptitSeb2025-03-081-2/+2
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* [ARM64_DYNAREC] Disabled inlined ClearCache as it seems not 100% efficientptitSeb2025-03-081-1/+3
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* Added F0 F7 /2 opcode ([ARM64_DYNAREC] too)ptitSeb2025-03-071-0/+28
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* [RV64_DYNAREC] Rollback some falsy optimization in the xtheadvector path (#2426)Yang Liu2025-03-072-4/+12
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* [ARM64_DYNAREC] Small change to AVX.66.0F 7F opcodeptitSeb2025-03-061-3/+3
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* [ARM64_DYNAREC] Added unaligned path for AVX.F3.0F 7F opcodeptitSeb2025-03-051-5/+24
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* [RV64_DYNAREC] Minor optimizations to sign mask extraction instructions for ↵Yang Liu2025-03-042-12/+5
| | | | vector (#2416)
* [RCFILE] Added range gdbjit support (#2414)Yang Liu2025-03-034-5/+5
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* [RV64_DYNAREC] Fixed some minor typos (#2406)Yang Liu2025-02-232-4/+2
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* [RV64_DYNAREC] Fixed swapCache scratch register usage (#2405)Yang Liu2025-02-231-9/+6
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* [ARM64_DYNAREC] Fixed potential issue with SUBSET with a DF still presentptitSeb2025-02-211-1/+1
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* [RV64_DYNAREC] Added more opcodes (#2400)Yang Liu2025-02-216-4/+76
| | | | | * [RV64_DYNAREC] Added more 66 0F 38 opcodes for vector * [RV64_DYNAREC] Added more opcodes
* [RV64_DYNAREC] Added more MMX opcodes for vector and fixes too (#2399)Yang Liu2025-02-212-18/+124
| | | | | * [RV64_DYNAREC] Fixed fallback to scalar messge * [RV64_DYNAREC] Added more MMX opcodes for vector and fixes too
* [ARM64_DYNAREC] More work on UD flagsptitSeb2025-02-202-69/+122
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* [ARM64_DYNAREC] Fixed a typo in flag computation for PCMPESTRI and BZHI opcodesptitSeb2025-02-202-2/+2
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* [ARM64_DYNAREC] Fixed a regression in LOCK XADD opcode (#2394)Yang Liu2025-02-201-0/+1
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* [BOX32][INTERP] Added some support for BOUND opcode ([ARM64_DYNAREC] too)ptitSeb2025-02-203-6/+37
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* [RCFILE] Added support for perfile dynarec dump (#2393)Yang Liu2025-02-1919-125/+125
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