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* [ARM64_DYNAREC] Removed many use of TABLE64 that would just slowdown build ↵ptitSeb2025-01-203-29/+12
| | | | of the dynablock for not much memory saved
* [ARM64_DYNAREC] Small optim for DB E2 opcodeptitSeb2025-01-191-3/+2
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* [ARM64_DYNAREC] Added 64/65 1B opcodeptitSeb2025-01-181-0/+11
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* [ARM64_DYNAREC] Fixed OF flags for rcr 8bits and 16bitsptitSeb2025-01-181-17/+12
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* [ARM64_DYNAREC] Fixed AVX.66.0F38 17 opcodeptitSeb2025-01-181-21/+22
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* [ARM64_DYNAREC] Fixed F0 0F BA opcodes with ip relative addressingptitSeb2025-01-181-4/+4
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* [RV64_DYNAREC] Refined printer for more thead instructions (#2272)Yang Liu2025-01-171-14/+557
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* [RV64_DYNAREC] Optimized 16bit constant RCL/RCR opcodes (#2270)Yang Liu2025-01-163-26/+120
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* [RV64_DYNAREC] Optimized 16bit constant ROR opcodes (#2268)Yang Liu2025-01-163-11/+51
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* [RV64_DYNAREC] Optimized 16bit constant ROL opcodes (#2267)Yang Liu2025-01-163-61/+124
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* [ARM64_DYNAREC] Removed an unused arg in SET_DFNONE (#2266)Yang Liu2025-01-1615-212/+219
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* [ARM64_DYNAREC] Added one more case of fastround=2 for AVX.F2.0F 5A opcodeptitSeb2025-01-151-1/+7
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* [ARM64_DYNAREC] Added unaligned code for F3 0F 7F opcodeptitSeb2025-01-151-2/+14
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* [ARM64_DYNAREC] Allow new ClearCache also for AndroidptitSeb2025-01-141-1/+1
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* [RV64_DYNAREC] Fixed simm12 overflow in some places ([LA64_DYNAREC] too) (#2264)Yang Liu2025-01-142-4/+4
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* [DYNAREC] Better handling of Clear Instruction Cache, also [ARM64_DYNAREC] ↵ptitSeb2025-01-141-3/+34
| | | | inlined instruction cache clear (but not for [ANDROID] to keep it safe)
* [RV64_DYNAREC] Fixed stack out of sync in native call (#2263)Yang Liu2025-01-141-0/+3
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* [RV64_DYNAREC] Fixed SET_ELEMENT_WIDTH (#2260)Yang Liu2025-01-143-19/+16
| | | ... also removed some unnecessary instructions in vector_loadmask
* Try to improve full x86 state gathering on SignalptitSeb2025-01-132-100/+199
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* [ARM64_DYNAREC] Better handling unaligned access to device memory, with ↵ptitSeb2025-01-1110-16/+95
| | | | regeration of code
* [RV64_DYNAREC] Fixed a 16bit SHR pastpath edge case (#2251)Yang Liu2025-01-111-3/+7
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* [BOX32] Improved elf memory managment for 32bits processptitSeb2025-01-111-1/+7
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* [RV64_DYNAREC] Disabled dynamic sew on MOVDQA as a workaround (#2249)Yang Liu2025-01-101-2/+2
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* [ARM64_DYNAREC] Reworked a bit DB / 7 opcodeptitSeb2025-01-101-56/+50
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* [ARM64_DYNAREC] Fixed SQXT(U)N printerptitSeb2025-01-101-1/+1
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* [RV64_DYNAREC] Fixed MOVMSKPS RVV 1.0 path (#2246)Yang Liu2025-01-091-1/+1
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* [RV64_DYNAREC] Fixed some typos (#2244)xctan2025-01-091-2/+2
| | | | | * [RV64_DYNAREC] Fixed CMPXCHG8B * [RV64_DYNAREC] Fixed typo
* [ARM64_DYNAREC] Small fixes for some 8bits OR and XOR opcodes on regs with ↵ptitSeb2025-01-081-4/+4
| | | | no flags (should help #2243 again)
* [ARM64_DYNAREC] Small fix for 80 /4 opcode on regs with no flags (should ↵ptitSeb2025-01-081-1/+2
| | | | help #2243)
* Port rounding of some x87 instructions from Box86 (#2242)Hagb (Junyu Guo 郭俊余)2025-01-086-9/+203
| | | | | | | | | | | * Port rounding of some x87 instructions from Box86 Ported from https://github.com/ptitSeb/box86/pull/951. The original pull request and this commit also contain some improvements on precision of `F2XM1` and `FYL2XP1`. * Run fpu_rounding test with dynarec only for ARM64 They have been implemented on dynarec only for ARM64.
* [ARM64_DYNAREC] Remove bloated x87 comp codeptitSeb2025-01-0815-76/+30
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* [INTERPRETER] Improved x87 emulation a bit ([ARM64_DYNAREC] too)ptitSeb2025-01-086-22/+42
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* [ARM64_DYNAREC] Added FCMEQ printerptitSeb2025-01-072-2/+8
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* [ARM64_DYNAREC]Small optimisation for 8bits and 16bits NOT opcode on registerptitSeb2025-01-073-6/+21
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* [ARM64_DYNAREC] Small optim to 8bits AND opcodes with constant and without flagsptitSeb2025-01-071-7/+31
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* [ARM64_DYNAREC] Optimized 8bits XOR when no flags is neededptitSeb2025-01-071-15/+56
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* [ARM64_DYNAREC] Optimized 8bits OR when no flags is neededptitSeb2025-01-072-15/+77
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* [DYNAREC] Imroved log on signal and flags/sse info gathering. ↵ptitSeb2025-01-054-9/+18
| | | | [ARM64_DYNAREC] Fixed some case of nat flags being incorectly used
* [INTERPRETER] Added a few more cpu extension and associated opcodes ↵ptitSeb2025-01-052-1/+36
| | | | ([ARM64_DYNAREC] added some of the new opcodes too)
* [ARM64_DYNAREC] Added a new emiterptitSeb2025-01-051-0/+1
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* [ARM64_DYNAREC] Small improvments on (V)PMOVMSKB opcodesptitSeb2025-01-052-18/+11
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* [ARM64_DYNAREC] Small optim on specific case of XOR with -1 constptitSeb2025-01-041-2/+6
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* [ARM64_DYNAREC] Don't simplify flags for add rsp, const when safeflags=2 is usedptitSeb2025-01-041-1/+1
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* [ARM64_DYNAREC] Small improvment on edge cases double to int x87 conversionsptitSeb2025-01-042-15/+28
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* [DYNAREC] Appended instruction name to symbol (#2228)Leslie Zhai2025-01-034-5/+5
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* [ARM64_DYNAREC] Small fixes to sse info retreiving on signalptitSeb2025-01-021-3/+2
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* [ARM64_DYNAREC] Fixed native flags with signal, and added sse handlingptitSeb2025-01-021-17/+51
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* [ARM64_DYNAREC] Change native flags handling in signal to make it more ↵ptitSeb2025-01-022-33/+186
| | | | extensible
* [ARM64_DYNAREC] Improved ADCX opcodeptitSeb2025-01-011-5/+19
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* [ARM64_DYNAREC] Improved native flags handlingptitSeb2025-01-011-14/+28
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