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* [RV64_DYNAREC] Added more LOCK prefix opcodes (#2169)Yang Liu2024-12-181-0/+79
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* [RV64_DYNAREC] Fixed 32bit ADDIz (#2168)Yang Liu2024-12-181-1/+9
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* [RV64_DYNAREC] Fixed CMPXCHG8B (#2167)Yang Liu2024-12-181-5/+5
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* [RV64_DYNAREC] Added unaligned support to CMPXCHG8B opcode (#2166)Yang Liu2024-12-183-69/+101
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* [GDBJIT] Refined RV64 and LA64 support (#2165)Yang Liu2024-12-183-4/+8
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* [LA64_DYNAREC] Added POPCNT opcode and fixed an issue too (#2164)Yang Liu2024-12-183-3/+55
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* [GDBJIT] Show x64pc in gdb, also added documentation (#2163)Yang Liu2024-12-181-1/+1
| | | | | | | | | * [GDBJIT] Show x64pc in gdb * Add env. variable and documentation * typo * oops
* Added initial GDBJIT support (#2162)Yang Liu2024-12-178-1/+29
| | | | | | | * Added GDBJIT support * fix * fix
* [RV64_DYNAREC] Extended simple wrapper for more int types (#2160)xctan2024-12-172-2/+9
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* [LA64_DYNAREC] Added PTEST opcode (#2158)Leslie Zhai2024-12-162-0/+35
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* [RV64_DYNAREC] Fixed more regressions (#2157)Yang Liu2024-12-152-5/+4
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* [RV64_DYNAREC] Optimize push/pop with xtheadmemidx (#2150)Yang Liu2024-12-131-28/+98
| | | | | * [RV64_DYNAREC] Optimize push/pop with xtheadmemidx * fix
* [RV64_DYNAREC] Fixed some TO_NAT usages (#2149)Yang Liu2024-12-131-4/+4
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* [RV64_DYNAREC] Reinitialize sew after callret (#2148)Yang Liu2024-12-131-27/+14
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* [RV64_DYNAREC] Reworked ZEROUP and freed t0 (#2147)xctan2024-12-1214-80/+74
| | | | | * [RV64_DYNAREC] Reworked ZEROUP and freed t0 * [RV64_DYNAREC] Removed the definition of xMASK
* [RV64_DYNAREC] New register mapping (#2139)Yang Liu2024-12-1223-595/+596
| | | | | * [RV64_DYNAREC] New register mapping * Fix
* [LA64_DYNAREC] Added more opcodes (#2145)Leslie Zhai2024-12-123-0/+64
| | | | | * [LA64_DYNAREC] Added more opcodes * [LA64_DYNAREC] Optimize MOVZX Gw, Eb
* [ARM64_DYNAREC] Force flags to be at least defered when priv opcode is run ↵ptitSeb2024-12-113-15/+75
| | | | on safeflags=2
* [DYNAREC] Small improvments on flags when end of block if trigger earlyptitSeb2024-12-112-5/+4
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* [ARM64_DYNAREC] Better hadnling of flags on btx opcode familly ([COSIM] and ↵ptitSeb2024-12-113-50/+222
| | | | improved undefined flags when running with cosim)
* [COSIM] Try to get more stable result on x87 stacks by unwinding status ↵ptitSeb2024-12-118-1/+44
| | | | before calling cosim
* [LA64_DYNAREC] Added more 660F opcodes (#2127)Leslie Zhai2024-12-103-1/+248
| | | | | | | | | | | | | * [LA64_DYNAREC] Added more 660F opcodes * [LA64_DYNAREC] Change VREPLGR2VR_D to VXOR_V * [LA64_DYNAREC] Optimize PMULHRSW Co-authored-by: Yang Liu <liuyang22@iscas.ac.cn> --------- Co-authored-by: Yang Liu <liuyang22@iscas.ac.cn>
* [INTERPRETER] Added 64bits 67 A1 opcode ([ARM64_DYNAREC] Too)ptitSeb2024-12-091-0/+10
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* [LA64_DYNAREC] Added AES opcodes (#2122)Leslie Zhai2024-12-071-0/+76
| | | | | * [LA64_DYNAREC] Added AES opcodes * [LA64_DYNAREC] Use LSX instruction instead
* [DYNAREC] Fixed a typo which leads to regression (#2121)Yang Liu2024-12-061-1/+1
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* [LA64_DYNAREC] Added XOR AX, Iw opcode (#2116)Leslie Zhai2024-12-061-0/+9
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* [RV64_DYNAREC] Improve native flag handlingptitSeb2024-12-067-39/+68
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* [LA64_DYNAREC] Added HLT opcode (#2112)Leslie Zhai2024-12-051-0/+11
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* [NON4KPAGE] Some more adjustments for non-4Kpagesize system (should help #2110)ptitSeb2024-12-051-3/+3
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* [DYNAREC] Introduced TO_NAT to ease register mapping changes in future (#2111)Yang Liu2024-12-0567-3960/+4558
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* Disable another execution test when pagesize is not 4KptitSeb2024-12-041-2/+2
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* Improved signal handling ([BOX32] Too)ptitSeb2024-12-031-4/+4
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* [LA64_DYNAREC] Fixed sign extension of 8-bit immediate in 66 opcodes (#2106)Yang Liu2024-12-031-19/+19
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* [RV64_DYNAREC] Added simple opcodes fusion as "native flags" (#2102)Yang Liu2024-12-0232-798/+1166
| | | | | | | * [RV64_DYNAREC] Added simple opcodes fusion as "native flags" * Disable 16bit CMOV * review
* [ARM64_DYNAREC] Improved some x87 opcode behaviourptitSeb2024-12-0216-45/+99
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* [LA64_DYNAREC] Added INSB, INSD, OUTSB and OUTSD opcodes (#2100)Leslie Zhai2024-12-021-0/+24
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* *[ARM64_DYNAREC] Fixed some cases of memory access on BTR/BTS opcodes (for ↵ptitSeb2024-12-012-4/+4
| | | | #2093)
* [ARM64_DYNAREC] Added F2 0F 80..8F opcodesptitSeb2024-11-301-0/+37
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* Added a new memExist helper function and use it instead of getMmapped were ↵ptitSeb2024-11-302-2/+4
| | | | it make sense
* [INTERPRETER] Added 0F 30 ocpode ([RM64_DYNAREC] too) (for #2090)ptitSeb2024-11-301-1/+11
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* [RV64] Added nan propagation emulation for interpreter and DynaRec (#2091)Yang Liu2024-11-284-125/+76
| | | | | * [RV64] Added nan propagation emulation for interpreter and DynaRec * oops
* [RV64_DYNAREC] Fix PTEST X_CF typo (#2088)Leslie Zhai2024-11-281-1/+1
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* [LA64_DYNAREC] Added LEA opcode (#2087)Leslie Zhai2024-11-281-0/+11
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* [RV64_DYNAREC] Fixed another regression in vector (#2086)Yang Liu2024-11-271-2/+2
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* [RV64_DYNAREC] Fixed more regressions for vector (#2082)Yang Liu2024-11-262-6/+6
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* [ARM64_DYNAREC][TRACE] Use BLR on ret/retn with TRACE to allow relevant ↵ptitSeb2024-11-261-0/+8
| | | | debug informations on bad returns
* [LA64_DYNAREC] Added SBB opcodes (#2076)Leslie Zhai2024-11-265-1/+115
| | | | | * [LA64_DYNAREC] Added SBB opcodes * [LA64_DYNAREC] clang-format and fix LOCK ADC wrong ed
* [RV64_DYNAREC] Fixed vector packed logical shift opcodes (#2075)xctan2024-11-262-3/+8
| | | | | * [RV64_DYNAREC] Fixed vector packed logical shift opcodes * [RV64_DYNAREC] Fixed a operand violation in vector CVTSD2SS
* [RV64_DYNAREC] Fixed vector SSE unpack opcodes (#2074)xctan2024-11-251-4/+4
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* [ARM64_DYNAREC] Added DYNAREC_PAUSE option for hint instructions (#2070)Yang Liu2024-11-258-7/+34
| | | | | | | | | | | * [ARM64_DYNAREC] Added DYNAREC_PAUSE option for hint instructions * Use sevl for wfe * Add docs * Fix typo * use switch case