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* [DYNAREC] Only test page protection when needed (and using a fester way) ↵ptitSeb2024-11-091-4/+12
| | | | (should address the performance regression of #2009)
* [RV64_DYNAREC] Added mmx infra for vector (#2011)Yang Liu2024-11-097-54/+185
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* [RV64_DYNAREC] Fixed some GETEX_vector usage (#2008)Yang Liu2024-11-081-3/+3
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* Added some weird 67 and 64/65 prefixed opcodes ([ARM64_DYNAREC] too)ptitSeb2024-11-072-0/+88
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* Added 64/65 69 opcode ([ARM64_DYNAREC] too)ptitSeb2024-11-071-0/+73
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* [ARM64_DYNAREC] Fixed some issue with frintts usesptitSeb2024-11-051-2/+2
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* [ARM64_DYNAREC] Fixed newly added frrintts useptitSeb2024-11-051-2/+2
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* [ARM64_DYNAREC] Reworked a bit FASTROUNDptitSeb2024-11-052-33/+45
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* [RV64_DYNAREC] Added more SSE opcodes for vector (#1999)Yang Liu2024-11-051-0/+25
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* Improve handling of memory protection, and excution bitptitSeb2024-11-042-1/+4
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* [DYNAREC] Reverted last 2 commit, will use CancelFillblock mecanism insteadptitSeb2024-11-036-131/+61
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* [LA64_DYNAREC] This should fix Loongarch dynarecptitSeb2024-11-031-0/+11
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* [DYNAREC] Make sure the emu structure is up-to-date each time LinkNext is calledptitSeb2024-11-036-61/+120
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* [ARM64_DYNAREC] Fixed an issue with native flags and opcode using C Helper ↵ptitSeb2024-11-031-5/+5
| | | | that use flags, like rcr and rcl
* [RV64_DYNAREC] Added more opcodes for vector (#1992)Yang Liu2024-11-012-0/+39
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* [RV64_DYNAREC] Added more opcodes for vector (#1991)Yang Liu2024-11-013-1/+67
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* [RV64_DYNAREC] Added more opcodes for vector (#1989)Yang Liu2024-11-013-0/+78
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* [RV64_DYNAREC] Added more opcodes for vector (#1987)Yang Liu2024-10-312-0/+125
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* Added 65 6C..6F opcodes ([ARM64_DYNAREC] too) (for #1985)ptitSeb2024-10-311-0/+24
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* [RV64_DYNAREC] Added more opcodes for vector (#1983)Yang Liu2024-10-302-0/+57
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* [Rv64_DYNAREC] Added more opcodes for vector (#1982)Yang Liu2024-10-302-0/+39
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* [RV64_DYNAREC] Added more opcodes for vector (#1981)Yang Liu2024-10-304-20/+109
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* [RV64_DYNAREC] Added more opcodes for vector (#1980)Yang Liu2024-10-303-22/+149
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* [RV64_DYNAREC] Added more opcodes for vector (#1979)Yang Liu2024-10-292-0/+72
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* [RV64_DYNAREC] Added more opcodes for vector (#1978)Yang Liu2024-10-292-2/+80
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* [ARM64_DYNAREC] Make sure neg on 16bits is correctly computedptitSeb2024-10-291-2/+3
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* [ARM64_DYNAREC] Fixed a potential issue with native flags used while some ↵ptitSeb2024-10-291-0/+5
| | | | intermediary opcode doesn't support it
* [ARM64_DYNAREC] Also use Native Carry flags directly when possibleptitSeb2024-10-2913-257/+443
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* [RV64_DYNAREC] Fixed 66 0F C2 CMPPD opcode for scalar and more (#1975)Yang Liu2024-10-295-10/+10
| | | | | * [RV64_DYNAREC] Fixed 66 0F C2 CMPPD opcode for scalar * more minor fixes
* [RV64_DYNAREC] Fixed MAXSS and MAXSD for vector (#1974)Yang Liu2024-10-282-12/+4
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* [RV64_DYNAREC] Added more opcodes for vector (#1972)Yang Liu2024-10-282-3/+119
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* [RV64_DYNAREC] Added more opcodes for vector (#1970)Yang Liu2024-10-284-31/+266
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* [RV64_DYNAREC] Added more opcodes for vector (#1969)Yang Liu2024-10-282-38/+81
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* [RV64_DYNAREC] Added more opcodes for vector (#1968)Yang Liu2024-10-283-47/+159
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* [RV64_DYNAREC] Added more opcodes for vector (#1966)Yang Liu2024-10-274-6/+76
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* [RV64_DYNAREC] Implemented the first AVX128 opcode for scalar only (#1962)Yang Liu2024-10-268-12/+368
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* [RV64_DYNAREC] Refined fpu_{push,pop}cache for vector (#1960)Yang Liu2024-10-261-57/+85
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* [RV64_DYNAREC] Added 1 more 66 0F opcode for vector (#1956)Yang Liu2024-10-246-58/+93
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* Make BOX64_IGNOREINT3 also ignore other privilged instructionsptitSeb2024-10-241-25/+36
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* [RV64_DYNAREC] Optimized horizontal opcodes (#1955)Yang Liu2024-10-241-20/+13
| | | Co-authored-by: xctan <xctan@cirno.icu>
* [Box64] Fix compilation issues (#1938) (#1952)Chi-Kuan Chiu2024-10-221-1/+2
| | | | | | | Fixed compilation errors related to variable declarations within switch-case statements without enclosing braces. This adjustment ensures compatibility with older versions of compiler. Resolves: #1938
* [ARM64_DYNAREC] Added AVX.F3.0F 53 opcodeptitSeb2024-10-221-0/+15
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* [ARM64_DYNAREC] More work around native flags handlingptitSeb2024-10-2010-165/+242
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* [ARM64_DYNAREC] Fixed edgecase on MINSS/MAXSS when comparing 0.0 and -0.0ptitSeb2024-10-201-2/+2
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* [ARM64_DYNAREC] Added BOX64_DYNAREC_NATIVEFLAGS to disable the use of native ↵ptitSeb2024-10-201-0/+2
| | | | flags, as there is still a bug or two in that mode (for #1947)
* [ARM64_DYNAREC] Some small improvment to a few shift opcode, to use flagless ↵ptitSeb2024-10-202-102/+60
| | | | jump when possible
* Improved 0F 0D opcode ([ARM64_DYNAREC] too) (FF7RI now have sound)ptitSeb2024-10-191-2/+13
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* [ARM64_DYNAREC] Fixed a regression with native flag commit (might help #1947)ptitSeb2024-10-181-0/+7
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* [ARM64_DYNAREC][TRACE] Update LR on jumpnext on trace build so debug info in ↵ptitSeb2024-10-181-1/+3
| | | | case of jump to NULL are accurate
* [ARM64_DYNAREC] Added directmapping of x86 flags to N, V and Z arm64 flagsptitSeb2024-10-1714-257/+897
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