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* [RV64_DYNAREC] Added a few more opcodes for vector (#1941)Yang Liu2024-10-152-0/+177
* [RV64_DYNAREC][LA64_DYNAREC] Fixed various issues (#1940)Yang Liu2024-10-1412-52/+57
* [INTERPRETER] Added 64/65 85 opcode ([ARM64_DYNAREC] too) (for #1932)ptitSeb2024-10-131-0/+11
* [RV64_DYNAREC] Fixed more issues for vector (#1928)Yang Liu2024-10-123-32/+55
* [RV64_DYNAREC] Fixed 66 0F 38 17 PTEST opcode for vector (#1927)Yang Liu2024-10-111-6/+6
* [RV64_DYNAREC] Fixed an issue in CVTTSD2SI for vector (#1925)Yang Liu2024-10-111-2/+2
* [RV64_DYNAREC] Split 660f.c to speedup compilation a bit (#1924)Yang Liu2024-10-114-1288/+1348
* [RV64_DYNAREC] Added more opcodes for vector (#1923)Yang Liu2024-10-113-11/+235
* [RV64_DYNAREC] Added more opcode for vector and some fixes too (#1920)Yang Liu2024-10-104-22/+57
* [ARM64_DYNAREC] Added a small optim for CALL 0 / POP reg type of sequenceptitSeb2024-10-101-1/+10
* [RV64_DYNAREC] Added more opcodes for vector (#1919)Yang Liu2024-10-101-0/+43
* [RV64_DYNAREC] Added more opcodes for vector (#1918)Yang Liu2024-10-103-0/+111
* [RV64_DYNAREC] Added 1 more opcode for vector, some fixes too (#1917)Yang Liu2024-10-103-28/+49
* [RV64_DYNAREC] Added more boilerplate for vector (#1916)Yang Liu2024-10-107-6/+340
* [RV64_DYNAREC] Added more opcodes and small optimizations (#1914)Yang Liu2024-10-083-2/+66
* [RV64_DYNAREC] Fixed CVTSS2SD and CVTSD2SS opcodes (#1913)Yang Liu2024-10-084-31/+83
* Added 66 6A opcode ([ARM64_DYNAREC] too) (for #1911)ptitSeb2024-10-071-0/+6
* [DYNAREC] Optimized CALL/RET RAS for out of dynablock jumps (#1909)Yang Liu2024-10-076-33/+93
* [ARM64_DYNAREC] Added 64 88 opcodeptitSeb2024-10-071-17/+52
* [DYNAREC] Tweaking indirect jumps for CALL/RET to use the return address stac...Yang Liu2024-10-065-26/+31
* [ARM64_DYNAREC] Worked on CF IRET opcodeptitSeb2024-10-043-3/+12
* [RV64_DYNAREC] Added more opcodes for xtheadvector (#1899)Yang Liu2024-10-033-79/+131
* [RV64_DYNAREC] Added more opcodes for xtheadvector and fixed more issues (#1897)Yang Liu2024-10-033-30/+106
* [DYNAREC] Added a new missing mode for fallback opcodes (#1896)Yang Liu2024-10-028-16/+16
* [RV64_DYNAREC] Added preliminary xtheadvector support (#1892)Yang Liu2024-10-0211-117/+314
* [RV64_DYNAREC] Eliminate redundant vsetvli by tracking its usage (#1886)Yang Liu2024-09-296-5/+20
* [RV64_DYNAREC] Minor optimization on vector_vsetvli (#1885)Yang Liu2024-09-292-4/+9
* [RV64_DYNAREC] Refined RISC-V vector emitter (#1884)Yang Liu2024-09-293-512/+510
* [RV64_DYNAREC] Refined RISC-V vector disassembler (#1880)xctan2024-09-271-584/+638
* [ARM64_DYNAREC] Small optim on 0F C7 /1 inst name (#1878)Yang Liu2024-09-261-1/+5
* [LA64_DYNAREC] Added unaligned support to CMPXCHG8B (#1877)Yang Liu2024-09-263-29/+79
* [LA64_DYNAREC] Fixed emit_add16 LBT implementation (#1875)Yang Liu2024-09-261-1/+1
* [LA64_DYNAREC][BOX32] Improved some 66 prefix opcodes (#1867)Yang Liu2024-09-252-14/+19
* [RV64_DYNAREC][BOX32] Added more opcodes (#1866)Yang Liu2024-09-242-8/+74
* [RV64_DYNAREC][BOX32] Improved some 66 prefix opcodes (#1865)Yang Liu2024-09-242-26/+31
* [LA64_DYNAREC][BOX32] Added more opcodes (#1864)Yang Liu2024-09-242-12/+99
* [ARM64_DYNAREC] Fixed some issue with a few 16bits opcodes on 64bits operationsptitSeb2024-09-241-10/+10
* [RV64_DYNAREC] Added more opcodes for vector (#1863)Yang Liu2024-09-242-1/+113
* [ARM64_DYNAREC] Fixed reset of rex on 67 prefixed opcodesptitSeb2024-09-241-2/+3
* [ARM64_DYNAREC] Added F1 opcodeptitSeb2024-09-241-0/+11
* [ARM64_DYNAREC] Added CA/CB ocpodesptitSeb2024-09-241-1/+29
* [ARM64_DYNAREC] Added 66 0F BF opcode (and cosmetic fix on interpreter)ptitSeb2024-09-241-0/+14
* [ARM64_DYNAREC] Added 64 A8 opcodeptitSeb2024-09-241-0/+9
* [ARM64_DYNAREC] Added 67 A9 opcode, and fixed 67 opcode with ignored REX prefixptitSeb2024-09-241-0/+9
* [RV64_DYNAREC] Fixed 66 0F 38 2B PACKUSDW opcode (#1861)Yang Liu2024-09-241-2/+1
* [RV64_DYNAREC] Added more opcodes for vector (#1857)Yang Liu2024-09-231-3/+63
* [RV64_DYNAREC] Added more opcodes for vector (#1855)Yang Liu2024-09-221-0/+41
* [RV64_DYNAREC] Added more opcodes for vector (#1853)Yang Liu2024-09-221-14/+55
* [RV64_DYNAREC] Added more opcodes for vector (#1852)Yang Liu2024-09-221-1/+161
* [RV64_DYNAREC] Added more opcode for vector and reinitialize sew after extern...Yang Liu2024-09-222-5/+48