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* [WOW64] Finished skeleton code for PE build (#2542)Yang Liu2025-04-171-1/+0
* [WOW64] More tweaks for PE build (#2528)Yang Liu2025-04-141-2/+3
* [INTERP] Fixed pure 32bits iretd not behaving correctlyptitSeb2025-04-131-16/+13
* Moved emit functions to seperate files from signals.h (#2516)Yang Liu2025-04-091-2/+2
* Decoupled alternate functions from bridge (#2500)Yang Liu2025-04-031-1/+1
* Moved more functions to os.h (#2497)Yang Liu2025-04-031-8/+3
* Moved some emit functions to os.h (#2494)Yang Liu2025-04-021-28/+28
* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-011-1/+1
* Added os.h for future usage (#2488)Yang Liu2025-04-011-0/+1
* [BOX32][INTERP] Added some support for BOUND opcode ([ARM64_DYNAREC] too)ptitSeb2025-02-201-3/+6
* [COSIM] Don't do div by 0 signal on interpreter part when testingptitSeb2025-02-021-0/+12
* [ENV] Initial refactor of env variables infrastructure (#2274)Yang Liu2025-01-211-5/+5
* [INTERPRETER] Added a check of CS validity on IRET opcodeptitSeb2025-01-061-27/+41
* Simplified ucontext uc_link managment (closer to glibc handling) ([BOX32] too)ptitSeb2024-12-201-14/+2
* Improved Signal handling ([ARM4_DYNAREC] too)ptitSeb2024-11-181-11/+18
* [INTERPRETER] Zero'd upper 32bits of regs when switching to 32bits from 64bitsptitSeb2024-11-151-21/+86
* Added some weird 67 and 64/65 prefixed opcodes ([ARM64_DYNAREC] too)ptitSeb2024-11-071-1/+1
* Added 64/65 D8..D9 opcodesptitSeb2024-11-071-4/+4
* Improve handling of memory protection, and excution bitptitSeb2024-11-041-5/+6
* Generate a SIGILL on unimplemented opcodeptitSeb2024-10-301-0/+1
* Make BOX64_IGNOREINT3 also ignore other privilged instructionsptitSeb2024-10-241-1/+16
* [INTERPRETER] Worked on CF IRET opcodeptitSeb2024-10-041-7/+9
* [INTEPRETER] Added a check on CS for CA/CB opecodesptitSeb2024-09-241-2/+10
* [CI] Refactored CI (#1795)Yang Liu2024-09-051-54/+1
* Added preliminary Box32 support (#1760)ptitSeb2024-08-261-1/+9
* Improved exception/int 3 handlingptitSeb2024-07-211-1/+12
* Improved TF handlingptitSeb2024-07-211-2/+3
* [INTERPRETER] Fixed some issue with INT opcodes and STEP logicptitSeb2024-07-171-3/+3
* Fixes (#1659)rajdakin2024-07-091-2/+2
* [INTERPRETER] opcode F1 is valid alson in 64bitsptitSeb2024-06-241-4/+0
* [INTERPRETER] Added 32bits F1 opcodeptitSeb2024-06-241-0/+10
* [COSIM] Some improvment to avoid segfault in edge casesptitSeb2024-06-171-1/+1
* [INTERPRETER] Added BMI1, BMI2 and ADX extensionsptitSeb2024-05-311-6/+6
* [ARM64_DYNAREC] Added a fisrt 128bits only AVX opcodeptitSeb2024-05-301-2/+0
* [INTERPRETER] Some fixes and small refactor on avx handlingptitSeb2024-05-271-23/+0
* [INTERPRETER] Added avx (66 0F 38) 00 opcodeptitSeb2024-05-271-1/+1
* [INTERPRETER] Added avx (66 0F 3A) 44 opcodeptitSeb2024-05-271-9/+9
* [INTERPRETER] my first avx opcodeptitSeb2024-05-261-4/+72
* [COSIM] Added thread-safe tests (#1477)Yang Liu2024-04-301-1/+52
* Fixed a few warning here and there...ptitSeb2024-04-131-122/+122
* POPF opcode should not overwrite IF bitptitSeb2024-03-081-1/+1
* [INTERPRETER] Generate a SIGILL when executing 3F opcode in 64bitsptitSeb2024-03-071-1/+1
* Added CA opcodeptitSeb2024-02-251-1/+14
* [32BITS] Added 0E opcode ([ARM64_DYNAREC] too)ptitSeb2024-02-241-0/+7
* [INTERPRETER] Added CB opcodeptitSeb2024-02-221-0/+12
* [INTERPRETER] CE opcode is only for 32bitsptitSeb2024-02-041-0/+4
* [INTERPRETER] Added CE opcodeptitSeb2024-01-311-1/+9
* [32BITS] Small improvment to E8/E9 opcode to trucate address to 32bitsptitSeb2024-01-291-2/+8
* [DYNAREC_TEST] Fixed some potential fals-positive on some CMP opcodesptitSeb2024-01-291-4/+4
* [TEST_DYNAREC] Improved accuracy of some tests, and avoid a some false-positiveptitSeb2024-01-271-3/+5