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* Improved Signal handling ([ARM4_DYNAREC] too)ptitSeb2024-11-181-11/+18
* [INTERPRETER] Zero'd upper 32bits of regs when switching to 32bits from 64bitsptitSeb2024-11-151-21/+86
* Added some weird 67 and 64/65 prefixed opcodes ([ARM64_DYNAREC] too)ptitSeb2024-11-071-1/+1
* Added 64/65 D8..D9 opcodesptitSeb2024-11-071-4/+4
* Improve handling of memory protection, and excution bitptitSeb2024-11-041-5/+6
* Generate a SIGILL on unimplemented opcodeptitSeb2024-10-301-0/+1
* Make BOX64_IGNOREINT3 also ignore other privilged instructionsptitSeb2024-10-241-1/+16
* [INTERPRETER] Worked on CF IRET opcodeptitSeb2024-10-041-7/+9
* [INTEPRETER] Added a check on CS for CA/CB opecodesptitSeb2024-09-241-2/+10
* [CI] Refactored CI (#1795)Yang Liu2024-09-051-54/+1
* Added preliminary Box32 support (#1760)ptitSeb2024-08-261-1/+9
* Improved exception/int 3 handlingptitSeb2024-07-211-1/+12
* Improved TF handlingptitSeb2024-07-211-2/+3
* [INTERPRETER] Fixed some issue with INT opcodes and STEP logicptitSeb2024-07-171-3/+3
* Fixes (#1659)rajdakin2024-07-091-2/+2
* [INTERPRETER] opcode F1 is valid alson in 64bitsptitSeb2024-06-241-4/+0
* [INTERPRETER] Added 32bits F1 opcodeptitSeb2024-06-241-0/+10
* [COSIM] Some improvment to avoid segfault in edge casesptitSeb2024-06-171-1/+1
* [INTERPRETER] Added BMI1, BMI2 and ADX extensionsptitSeb2024-05-311-6/+6
* [ARM64_DYNAREC] Added a fisrt 128bits only AVX opcodeptitSeb2024-05-301-2/+0
* [INTERPRETER] Some fixes and small refactor on avx handlingptitSeb2024-05-271-23/+0
* [INTERPRETER] Added avx (66 0F 38) 00 opcodeptitSeb2024-05-271-1/+1
* [INTERPRETER] Added avx (66 0F 3A) 44 opcodeptitSeb2024-05-271-9/+9
* [INTERPRETER] my first avx opcodeptitSeb2024-05-261-4/+72
* [COSIM] Added thread-safe tests (#1477)Yang Liu2024-04-301-1/+52
* Fixed a few warning here and there...ptitSeb2024-04-131-122/+122
* POPF opcode should not overwrite IF bitptitSeb2024-03-081-1/+1
* [INTERPRETER] Generate a SIGILL when executing 3F opcode in 64bitsptitSeb2024-03-071-1/+1
* Added CA opcodeptitSeb2024-02-251-1/+14
* [32BITS] Added 0E opcode ([ARM64_DYNAREC] too)ptitSeb2024-02-241-0/+7
* [INTERPRETER] Added CB opcodeptitSeb2024-02-221-0/+12
* [INTERPRETER] CE opcode is only for 32bitsptitSeb2024-02-041-0/+4
* [INTERPRETER] Added CE opcodeptitSeb2024-01-311-1/+9
* [32BITS] Small improvment to E8/E9 opcode to trucate address to 32bitsptitSeb2024-01-291-2/+8
* [DYNAREC_TEST] Fixed some potential fals-positive on some CMP opcodesptitSeb2024-01-291-4/+4
* [TEST_DYNAREC] Improved accuracy of some tests, and avoid a some false-positiveptitSeb2024-01-271-3/+5
* [32BITS] Added 16/17 ocodes ([ARM64_DYNAREC] too)ptitSeb2024-01-261-0/+16
* Added a new option BOX64_MMAP32 to use 32bits mapping on external MMAP (help ...ptitSeb2024-01-231-0/+17
* Fixes (#1207)rajdakin2024-01-181-2/+7
* [INTERPRETER] Fixed D7 opcodeptitSeb2024-01-161-4/+1
* [INTERPRETER] Fixed VM Detection (TF trick) for interpreterptitSeb2024-01-151-3/+12
* Better way to handle multiple 3E/26 and F2/F3 prefixes ([DYNAREC] too)ptitSeb2023-12-071-4/+7
* [INTERPRETER] Added addling to divide by 0 exceptionptitSeb2023-12-051-0/+12
* [INTERPRETER] Call opcode also need getAlternate redirectionptitSeb2023-12-051-0/+1
* [DYNAREC][INTERPRETER] Rework on 6C/6D/6E/6F opcodes (#1098)Yang Liu2023-11-281-71/+6
* [INTERPRETER] LES/LDS are valid only if next byte has high bit not setptitSeb2023-11-231-2/+2
* [INTERPRETER] Fixed some rare issue with XLAT ocpodeptitSeb2023-11-201-1/+4
* Saved defered flag status when processing signal / foreign functionptitSeb2023-11-171-1/+1
* Use non-atomic operation on XCHG when unalignedptitSeb2023-11-081-1/+7
* Added a workaround for unalinged 32bits xchgptitSeb2023-10-231-1/+7