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path: root/src/emu/x64run0f.c (follow)
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* Fixed 0F E3 opcodeptitSeb2021-04-111-6/+3
* Added 0F DE opcodeptitSeb2021-04-111-1/+7
* Added 0F DA ocode ([DYNAREC] too)ptitSeb2021-04-071-1/+7
* Added 0F E0 opcode ([DYNAREC] too)ptitSeb2021-04-021-1/+7
* Added 0F E7 opcode ([DYNAREC] too)ptitSeb2021-04-021-1/+9
* Try to add 0F AE /7 CLFLUSH opcodeptitSeb2021-04-011-0/+5
* Added 0F 31 opcode ([DYNAREC] too)ptitSeb2021-04-011-0/+6
* Fixed 0F 7E opcode, plus a few other small changesptitSeb2021-04-011-16/+19
* Added 0F 38 00/04/0B/1C/1D/1E opcodesptitSeb2021-03-311-0/+63
* Added 0F 70/C4/C5/F6 opcodesptitSeb2021-03-301-2/+33
* Added 0F 71/72/73 opcodesptitSeb2021-03-301-0/+74
* Try to sistematicaly erase upper RAX on cmpxchg opcodeptitSeb2021-03-291-2/+1
* Added 0F 18 opcodeptitSeb2021-03-261-0/+16
* Added 0F 6E opcodeptitSeb2021-03-261-0/+9
* Renamed arm64_lock_helper to arm64_lockptitSeb2021-03-201-1/+1
* [DYNAREC] Added Basic blocks for dynarecptitSeb2021-03-141-1/+1
* Added a few more SSE opcodesptitSeb2021-03-131-0/+6
* Added a bunch of SSE2 opcodesptitSeb2021-03-121-2/+101
* Added a large number of CPU opcodesptitSeb2021-03-121-4/+92
* Added and fixed many opcodesptitSeb2021-03-101-11/+176
* Added a bunch of various opcodesptitSeb2021-03-101-0/+28
* Added REX 0F BA opcodesptitSeb2021-03-091-0/+97
* Added REX 0F 5A..5F opcodesptitSeb2021-03-091-1/+48
* Added REX 0F C8..CF BSWAP opcodesptitSeb2021-03-091-0/+15
* Added 0F AE /2 and /3 opcodesptitSeb2021-03-081-0/+6
* More 0F and 66 0F opcodesptitSeb2021-03-081-0/+44
* Added a gew more various opcodesptitSeb2021-03-081-0/+71
* Added a few SSE opcodesptitSeb2021-03-071-0/+19
* Added another batch of MMX opcodes (mmx test is ok)ptitSeb2021-03-071-1/+131
* Added a new batch of MMX opcodesptitSeb2021-03-071-3/+153
* Added some MMX opcodes and fixed 66 0F 7E MOVQptitSeb2021-03-071-0/+87
* Added another batch of MMX opcodesptitSeb2021-03-071-0/+42
* Added 0F EC opcodeptitSeb2021-03-071-0/+10
* Added a bunch of MMX and SSE opcodesptitSeb2021-03-071-1/+45
* Fixed mod/rm relative computation when opcode have trailing bytesptitSeb2021-03-061-11/+11
* Added 0F 11 MOVUPS opcodeptitSeb2021-03-061-0/+7
* Added (partial) 0F AE (M/S/L)FENCE opcodesptitSeb2021-03-061-0/+17
* Added REX 0F 90..9F SETcc opcodeptitSeb2021-03-061-0/+8
* Added REX 0F 29 MOVAPS ocpodeptitSeb2021-03-061-1/+10
* Added 0F A2 cpuid opcodeptitSeb2021-03-061-1/+7
* Added REX 0F B7 MOVZX opcodeptitSeb2021-03-051-0/+6
* Added 0F BE/BF MOVSX opcodesptitSeb2021-03-051-0/+23
* Ajusted REX 0F B6 opcode, as 32bits access to regs always wipe upper partptitSeb2021-03-051-4/+1
* Added REX 0F 80..8F Jcc opcodesptitSeb2021-03-051-0/+6
* Added REX 0F B6 MOVZX opcodeptitSeb2021-03-051-1/+10
* Added REX 0F 40..4F CMOVcc opcodesptitSeb2021-03-051-21/+11
* Added REX 0F AF IMUL opcodesptitSeb2021-03-051-3/+12
* Added 0F 05 SYSCALL opcode (and test01 works now)ptitSeb2021-03-041-0/+4
* Added 0F 1F NOP opcodeptitSeb2021-03-041-0/+70