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* Decoupled alternate functions from bridge (#2500)Yang Liu2025-04-031-1/+1
* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-011-1/+1
* Added 66 6A opcode ([ARM64_DYNAREC] too) (for #1911)ptitSeb2024-10-071-1/+4
* [CI] Refactored CI (#1795)Yang Liu2024-09-051-3/+0
* [INTERPRETER] Added 64 66 8D opcode (#1648)Haichen Wu2024-07-061-3/+3
* Added 66 F2/F3 A4 opcode ({DYNAREC] too)ptitSeb2024-06-221-1/+14
* [COSIM] Added thread-safe tests (#1477)Yang Liu2024-04-301-0/+3
* Added 66 68 opcode ([ARM64_DYNAREC] too)ptitSeb2024-04-171-0/+4
* Fixed a few warning here and there...ptitSeb2024-04-131-84/+84
* Added 66 F8/F9 ([ARM64_DYNAREC] too)ptitSeb2024-03-011-0/+8
* Added 66 8F opcode ([ARM64_DYNAREC] too)ptitSeb2024-01-261-1/+5
* [INTERPRETER] Ignore 36/26 segment prefix for 66 prefixed opcodesptitSeb2024-01-261-1/+1
* Fixes (#1207)rajdakin2024-01-181-1/+2
* Added/Fix some 16bits PUSH POP opcode ([ARM64_DYNAREC] too) (for DaveTheDiver...ptitSeb2023-12-211-18/+9
* [INTERPRETER] Made some opcode truer to what they should on some edge casesptitSeb2023-12-061-2/+2
* [32BITS] Forgot 66 54 opcodeptitSeb2023-12-051-0/+1
* Added 66 0F F2 38 F1 opcode, and fixed all 66 0F F2/F3 xx opcodes (should hel...ptitSeb2023-11-041-5/+20
* [32BITS] Added a few 66 opcodes ([ARM64_DYNAREC] too)ptitSeb2023-10-261-0/+6
* [32BITS] Added 66 06/07 and 66 1E/1F opcodes ([ARM64_DYNAREC] too)ptitSeb2023-10-241-0/+28
* [32BITS] Added 66 50-5F opcodes ([ARM64_DYNAREC] too, and fixed 66 61 opcode)ptitSeb2023-07-231-21/+46
* [32BITS] Added 66 FF /6 opcode ([ARM64_DYNAREC] too)ptitSeb2023-07-231-4/+6
* Added 66 9C/9D opcodes (mostly for 32bits)ptitSeb2023-07-141-0/+10
* A few Push/Pop fixes and cleanups (#878)Alexandre Julliard2023-07-031-2/+2
* [32BITS] Added 66 60/61 opcodes (for #865)ptitSeb2023-06-261-22/+52
* Comment fix on 66 AF opcode nameptitSeb2023-06-251-1/+1
* [32BITS] Added 66 40..4F opcodesptitSeb2023-06-231-0/+23
* [32BITS] Various small fixes in 32bits interpreterptitSeb2023-06-181-5/+3
* [32BITS] Fixed some issue reading rex in 32bits modeptitSeb2023-06-181-4/+5
* [32BITS] Fixed an issue with 66 A1/A3 opcodesptitSeb2023-06-181-8/+16
* Added some support for 32bits code (doesn't seems enough for wow64 yet)ptitSeb2023-06-181-3/+11
* [DYNAREC] Cleaned up the TEST_INTERPRETER a bitptitSeb2023-03-281-7/+3
* [DYNAREC] Added BOX64_DYNAREC_TEST to run interpeter and dynarec at the same ...ptitSeb2023-03-271-1/+40
* Various small fixes on InterpretorptitSeb2023-02-161-1/+3
* Chenged Interpretor so RIP is updated on opcode success (better precision for...ptitSeb2022-08-061-15/+14
* Various improvement and some workaround to support musl binary (for #324)ptitSeb2022-07-091-1/+6
* Various small fixes and warning removalptitSeb2022-04-111-6/+6
* Added 66 (2E) 70-7F opcodes ([DYNAREC] too) (for #271)ptitSeb2022-04-061-0/+20
* [DYNAREC] Refactored dynarec to ease the future adding of new target architec...ptitSeb2022-02-271-1/+1
* Added 66 8C opcode (for #61)ptitSeb2021-07-161-1/+8
* Added 66 90-97 opcodes ([DYNAREC] too) (for #44)ptitSeb2021-07-091-1/+21
* Removed an out-of-place commentptitSeb2021-07-091-1/+1
* Added 66 A1/A3 opcodes ([DYNAREC] too)ptitSeb2021-06-021-0/+14
* Added 66 F0 83 opcodeptitSeb2021-04-241-0/+3
* Added 66 8D and 66 E8 opcodeptitSeb2021-03-261-0/+17
* Added 66 8B opcode (was already in dynarec)ptitSeb2021-03-261-1/+14
* Renamed arm64_lock_helper to arm64_lockptitSeb2021-03-201-1/+1
* [DYNAREC] Added Basic blocks for dynarecptitSeb2021-03-141-2/+1
* Added a bunch of SSE opcodesptitSeb2021-03-131-0/+7
* Added a large number of CPU opcodesptitSeb2021-03-121-4/+257
* Added more x87 opcodesptitSeb2021-03-111-0/+6