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* [INTERP] Fex fixes and small cosmetic changes to some partial (V)MOV opcodesptitSeb2025-04-231-12/+20
* [INTERP] Improved (V)[MIN/MAX][S/P][S/D] opcodesptitSeb2025-04-221-4/+4
* [INTERP] More fixes to INSERTQ/EXTRQ opcodesptitSeb2025-04-211-4/+6
* [INTERP] Fixed EXTRQ opcodeptitSeb2025-04-211-3/+3
* Moved emit functions to seperate files from signals.h (#2516)Yang Liu2025-04-091-1/+1
* [INTERP] Small changes in a few SSE/AVX convertions opcodesptitSeb2025-04-041-2/+2
* [INTERP] Better handling of default NAN for a few opcodes, more to comeptitSeb2025-04-031-43/+10
* Moved some emit functions to os.h (#2494)Yang Liu2025-04-021-3/+4
* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-011-1/+0
* [INTERP] Added more nops ([DYNAREC] too) (#2378)Yang Liu2025-02-171-0/+1
* [INTERP] Added 66 0F 19 NOP opcode ([DYNAREC] too) (#2375)Yang Liu2025-02-171-0/+1
* [INTERPRETER] Fixed a few warningptitSeb2025-01-261-4/+4
* [ENV] Initial refactor of env variables infrastructure (#2274)Yang Liu2025-01-211-4/+4
* [INTERPRETER] Added a few more cpu extension and associated opcodes ([ARM64_D...ptitSeb2025-01-051-1/+41
* [INTERPRETER] Fixed 32bits ADCX/ADOX opcodesptitSeb2024-12-281-1/+2
* [INTERPRETER] Exposed SSE4a for CPUTYPE=1, implemented all 4 opcodesptitSeb2024-12-271-0/+33
* [INTERP] Fixed overflow checking for convertion opcodes (#1976)Yang Liu2024-10-291-2/+2
* [ARM64_DYNAREC] Added 66 0F BF opcode (and cosmetic fix on interpreter)ptitSeb2024-09-241-2/+2
* [RV64_DYNAREC] Added more opcodes (#1740)Yang Liu2024-08-161-2/+2
* Fixes (#1659)rajdakin2024-07-091-15/+15
* [COSIM] Some improvment to avoid segfault in edge casesptitSeb2024-06-171-1/+1
* [INTERPRETER] Small fixes for some rare case of AES with serc==destptitSeb2024-06-021-19/+19
* [INTERPRETER] Added BMI1, BMI2 and ADX extensionsptitSeb2024-05-311-1/+27
* [INTERPRETER] Added more avx/avx2 opcodes, and fixed vpxorptitSeb2024-05-291-28/+12
* [INTERPRETER] Even more avx/avx2 opcodes, all the mov and moreptitSeb2024-05-281-1/+0
* [INTERPRETER] Some fixes when opcode use with same reg as src and destptitSeb2024-05-271-0/+8
* [INTERPRETER] Fixed pcmp[ei]strm opcodesptitSeb2024-04-281-8/+8
* Added 66 0F BF opcodeptitSeb2024-03-211-0/+9
* [INTERPRETER] Fixed a typo in 66 0F 2C opcodeptitSeb2023-11-101-4/+4
* Cosmetic changeptitSeb2023-11-071-1/+1
* Fixed a comment for 66 0F 3A 62 opcodeptitSeb2023-10-301-1/+1
* Added full SSE 4.2 supportptitSeb2023-10-301-0/+60
* [INTERP] Fix fpu_round (#1030)Yang Liu2023-10-251-6/+31
* Added 66 0F 3A 0D opcode ([ARM64_DYNAREC] Too)ptitSeb2023-09-261-1/+10
* [RV64_DYNAREC] Added more support for XTheadBb extension (#989)Yang Liu2023-09-241-24/+24
* [RV64_DYNAREC] Added movbe opcodewannacu2023-08-071-1/+12
* [INTERPRETER] Added 66 0F 38 37 PCMPGTQ opcode (#827)Yang Liu2023-06-081-1/+7
* Added 66 0F 38 07 opcode ([ARM64_DYNAREC] too)ptitSeb2023-04-081-1/+17
* Added 66 0F 38 2A opcode ([ARM64_DYNAREC] too)ptitSeb2023-04-081-1/+7
* Added 66 0F 38 41 opcodeptitSeb2023-04-081-0/+17
* Added 66 0F 3A 41 opcodeptitSeb2023-04-081-0/+14
* Fixed 66 0F 38 40 opcodeptitSeb2023-04-081-2/+1
* Added 66 0F 38 28 opcode ({ARM64_DYNAREC] too)ptitSeb2023-04-081-0/+7
* Added 66 0F 3A 42 opcodeptitSeb2023-04-081-0/+21
* Added 66 0F 38 06 opcodeptitSeb2023-04-081-0/+13
* Fixed 66 0F 3A 08/09/0A/0B opcodeptitSeb2023-04-081-5/+5
* Added 66 0F 38 15 opcodeptitSeb2023-04-081-0/+9
* Added 66 0F 38 0C opcode ([ARM64_DYNAREC] too)ptitSeb2023-04-081-0/+11
* Fixed 66 0F 38 2B opcodeptitSeb2023-04-081-3/+3
* Added back some isnan testing to integer conversion (converting a nan, infini...ptitSeb2023-04-061-17/+20