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* [DYNACACHE] Refactored cpu extension, will be used in dynacache signature checksptitSeb2025-06-141-1/+1
* [WOWBOX64] Fixed a few more warningsptitSeb2025-06-141-2/+2
* [WOWBOX64] Fixed a few warningsptitSeb2025-06-141-6/+6
* [DYNACACHE] Created a const table, for later use in internal relocation ([ARM...ptitSeb2025-06-131-2/+2
* [WRAPPER] Wrapped a few more functions in gio2 and libresolv (#2737)Yang Liu2025-06-131-0/+2
* [WRAPPER] Added 2 more functions to libc (for #2731) (#2733)Yang Liu2025-06-121-0/+2
* [INTERP] Fixed 64/65 67 64bit rex decoding (#2729)Yang Liu2025-06-121-0/+5
* [TRACE] Bring back in-house zydis header for v3.x (#2727)Yang Liu2025-06-112-0/+4404
* [TRACE] Added support for libzydis v4.x and removed the in-house zydis header...Yang Liu2025-06-092-4461/+124
* [INTERP] Added 64/65 0F BF opcode (for #2716)ptitSeb2025-06-091-0/+18
* Fixed a regression on syscallptitSeb2025-06-051-1/+1
* [TRACE][BOX32] Fixed some and cleaup detailed function call traceptitSeb2025-06-021-28/+32
* [WRAPPER] Fixed some xcb-image wrappings (#2697)Yang Liu2025-06-011-2/+0
* Merge pull request #2692 from ksco/wow64André Zwing2025-05-301-0/+2
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| * [WOW64] Improved RIP handling on INT nYang Liu2025-05-311-0/+2
* | [ARM64_DYNAREC] Try to optimise Windows INT n version on 64bits (TODO: Interp...ptitSeb2025-05-302-1/+6
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* [WOW64] Added more missing pieces and the interpreter works (#2682)Yang Liu2025-05-291-0/+6
* [INTERP] Added 64/65 67 89/8B 64bits opcodesptitSeb2025-05-285-2/+105
* [INTERP] Added unaligned path for F0 FF /1 32bits opcodeptitSeb2025-05-211-3/+14
* [INTERP] Small change on 0F 2E/2F opcode, and alows Interp->Dynarec on 80..8F...ptitSeb2025-05-201-2/+2
* [INTERP] Fixed D9 F5/F8 (for #2644)ptitSeb2025-05-201-40/+14
* [WOW64] Implement BTCpuSimulateAndré Zwing2025-05-191-0/+3
* [DOCS] Align usage.json and env.h (#2633)Yang Liu2025-05-142-28/+18
* [WRAPPER] Added more wrapped function to ffmpeg, and disable it with NOGTK=1,...ptitSeb2025-05-111-0/+20
* [WRAPPER] Added a few more wrapped function to ffmpegs libsptitSeb2025-05-091-0/+2
* [TRACE] Better log for unsetenv and putenv functionsptitSeb2025-05-031-0/+4
* [INTERP] Added missing opcode nae in commentptitSeb2025-05-011-2/+2
* [INTERP] Fixed edge-case for VPERM2[F/I]128 opcodesptitSeb2025-05-011-4/+4
* [INTERP] VMASKMOVP[S/D] opcodes have no register only pathptitSeb2025-05-011-0/+8
* [INTERP] Fixed another instruction name commentptitSeb2025-04-301-1/+1
* [INTERP] Improved NAN handling on VSUBPD opcodeptitSeb2025-04-301-0/+4
* [INTERP] Improved NAN handling for some (V)SQRTS[S/D] opcodesptitSeb2025-04-304-2/+12
* [INTERP] Improve NAN handling on SQRTPS opcodeptitSeb2025-04-301-2/+4
* [INTERP] Improved (V)RSQRTSS opcodesptitSeb2025-04-292-3/+20
* [INTERP] Fixed some more instruction name commentsptitSeb2025-04-291-2/+2
* [INTERP] Fixes and improvments to SSE/AVX packed shift opcodesptitSeb2025-04-283-84/+40
* [INTERP] More work on UD flagsptitSeb2025-04-275-13/+65
* [INTERP] Fixed some potential issue with LOCK ADC/SBB on Dynarec buildptitSeb2025-04-271-15/+23
* [INTERP] Added 66 F3 0F BC opcodeptitSeb2025-04-271-0/+33
* [WRAPPER] Reworked libssh2 wrapping, to make it more completeptitSeb2025-04-271-0/+38
* [INTERP] Cosmetic change to VPSHUFD opocdeptitSeb2025-04-261-1/+1
* [WRAPPER] Added some missing function to wrapped libgio-2 (for #2575)ptitSeb2025-04-261-0/+4
* [INTERP] Another fix for a opcode name in commentptitSeb2025-04-251-1/+1
* [INTERP] Fixed a small issue where VPCMP[E/I]STRM would not wipe upper 128bit...ptitSeb2025-04-251-2/+2
* [INTERP] Yet another opcode name comment fixptitSeb2025-04-241-1/+1
* [INTERP] Cosmetic change to 0F 1C..1E opcodesptitSeb2025-04-241-3/+3
* [INTERP] Added nan handling on AVX.F3.0F 59 opcodeptitSeb2025-04-241-0/+2
* [INTERP] Fixed another opcode name commentptitSeb2025-04-241-1/+1
* [INTERP] Fixed a commentptitSeb2025-04-241-1/+1
* [INTERP] Small change to various (V)MOVNT* opcodes, forbidding reg -> reg formptitSeb2025-04-246-56/+74