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* [ARM64_DYNAREC] Empty regs needs to be fetched last (again)ptitSeb2024-06-031-42/+14
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* [ARM64_DYNAREC] Fixed AVX Cache transform between internal jump pointsptitSeb2024-06-032-5/+7
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* [COSIM] Added more helpers to avoid segfault on rare casesptitSeb2024-06-034-8/+11
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* [ARM64_DYNAREC] Empty register needs to be fetched lastptitSeb2024-06-031-17/+9
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* [INTERPRETER] Fixed VZEROUPPER opcodeptitSeb2024-06-031-1/+1
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* Try to fix mmap64 already defined error in custommem.c (#1552)Romain TISSERAND2024-06-032-26/+49
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* [ARM64_DYNAREC] Added AVX.F3.0F 52, AVX.66.0F E4 and AVX.0F 52 opcodesptitSeb2024-06-023-0/+59
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* [ARM64_DYNAREC] Added AVX.66.0F38 08-0A/1C-1E/30-35/58/59/90/92/A8/A9/B8/B9 ↵ptitSeb2024-06-024-5/+366
| | | | opcodes
* [ARM64_DYNAREC] Remove parasite typo to fix buildptitSeb2024-06-021-1/+1
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* [INTERPRETER] Added missing FMA opcodes, and fixed some existing onesptitSeb2024-06-021-12/+156
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* [INTERPRETER] Fixed opcode name in commentptitSeb2024-06-021-3/+3
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* [ARM64_DYNAREC] Added AVX.66.0F D6/E5/E7/F5 opcodesptitSeb2024-06-021-1/+66
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* [ARM64_DYNAREC] Added AVX.66.0F3A 00/01/04/05/0A/0B/46 opcodesptitSeb2024-06-021-0/+126
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* [ARM64_DYNAREC] Fixed handling of YMM0 on forward jumpptitSeb2024-06-023-3/+7
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* [COSIM] Fixed YMM handling in cosim, seems to work better nowptitSeb2024-06-023-1/+16
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* [ARM64_DYNAREC] Added AVX.66.0F 60-63/67-6A/71 opcodesptitSeb2024-06-021-4/+163
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* [ARM64_DYNAREC] Don't use fix scratch for x87 conversion, it might conflict ↵ptitSeb2024-06-023-17/+36
| | | | with YMM handling
* [INTERPRETER] Small cosmetic changes on raz of ymmptitSeb2024-06-021-9/+9
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* [COSIM] Improved reliability with AVX (but there is still something wrong there)ptitSeb2024-06-022-14/+15
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* [INTERPRETER] Added FMA cpu extension (linked to BOX64_AVX=2)ptitSeb2024-06-023-2/+449
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* [ARM64_DYNAREC] Fixed YMM COSIM refreshing on each stepsptitSeb2024-06-021-3/+3
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* [COSIM] Fixed issue with YMM printing on differenceptitSeb2024-06-021-1/+1
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* [LA64_DYNAREC] Added more opcodes (#1549)Yang Liu2024-06-029-0/+654
| | | | | * [LA64_DYNAREC] Added more opcodes * fastnan handling and fixed PALIGNR...
* [ARM64_DYNAREC] Added AVX.66.0F3A 21 and fixed a bunch of issuesptitSeb2024-06-025-21/+62
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* [INTERPRETER] Small fixes for some rare case of AES with serc==destptitSeb2024-06-021-19/+19
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* [LA64_DYNAREC] Added more opcodes and fixed ADC opcode (#1548)Yang Liu2024-06-013-19/+67
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* [ARM64_DYNAREC] Added AVX.F2.0F 58-5A/5C-5F opcodesptitSeb2024-06-011-0/+123
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* [ARM64_DYNAREC] Added AVX.66.0F C4/C5/D7 opcodesptitSeb2024-06-012-0/+81
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* [ARM64_DYNAREC] Added BMI.F2.0F38 F7 opcodeptitSeb2024-06-011-0/+9
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* [ARM64_DYNAREC] Added AVX.66.0F 10-17/29/29/2B/2E/2F/54-59/74-76/7E opcodesptitSeb2024-06-012-2/+325
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* [ARM64_DYNAREC] Added AVX.0F 28/29/2B/2E/2F/54-56/5A-5F opcodes, plus ↵ptitSeb2024-06-013-7/+201
| | | | various small fixes
* [INTERP] Rework on the 16b emulation for LA64 (#1547)Yang Liu2024-06-014-32/+34
| | | | | * [INTERP] Rework on the 16b emulation for LA64 * fix compiler issue
* [ARM64_DYNAREC] Added AVX.F3.0F 10-12/16/2A/2C/2D/58-5F opcodes, plus a few ↵ptitSeb2024-06-016-7/+299
| | | | other fixes
* [ARM64_DYNAREC] Added AVX.F2.0F 10-12/2A/2C/2D opcodesptitSeb2024-06-015-7/+205
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* [ARM64_DYNAREC] Added a few 67 prefixed opcodesptitSeb2024-06-014-0/+181
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* [ARM64_DYNAREC] Added ADX RORX opcodeptitSeb2024-06-013-0/+81
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* [ARM64_DYNAREC] Added AVX.66.0F3A 38/39 opcodesptitSeb2024-06-011-2/+4
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* [ARM64_DYNAREC] Added AVX.66.0F 72/7F/F8-FEptitSeb2024-06-012-0/+162
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* [ARM64_DYNAREC] Added AVX.F3.0F 7E opcodeptitSeb2024-06-011-0/+15
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* Detects extensions even if dynarec is disable at runtime (#1546)Yang Liu2024-06-011-2/+0
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* [ARM64_DYNAREC] Added AVX.66.0F38 00/DC-DF opcodesptitSeb2024-06-013-21/+256
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* [ARM64_DYNAREC] Fix issue with 66 0F 38 DC-DF when rare case of dest==srcptitSeb2024-06-011-8/+24
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* [ARM64_DYNAREC] Added AVX.F3.0F 7F opcodeptitSeb2024-06-011-1/+24
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* [ARM64_DYNAREC] Added a couple of AVX.66.0F3A opcodes, and fixed some ↵ptitSeb2024-06-016-4/+145
| | | | sse/avx function helpers
* [ARM64_DYNAREC] Added some AVX.66.0F opcodesptitSeb2024-06-012-1/+308
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* [LA64_DYNAREC] Added LOCK CMPXCHG unaligned version (#1545)Yang Liu2024-06-012-3/+24
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* [RV64_DYNAREC] Fixed LOCK CMPXCHG unaligned version (#1544)Yang Liu2024-06-011-4/+4
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* [LA64_DYNAREC] Fixed 0F C2 CMPPS opcode (#1543)Yang Liu2024-05-311-8/+8
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* [ARM64_DYNAREC] Added a bunch of AVX/BMI2/ADX opcodesptitSeb2024-05-318-20/+456
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* [INTERPRETER] Added BMI1, BMI2 and ADX extensionsptitSeb2024-05-3118-23/+905
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