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* [RV64_DYNAREC] Added {C1,D1} /{5,7} opcode and some fixes (#569)xctan2023-03-164-4/+99
| | | | | * [RV64_DYNAREC] Added C1 /5 SHR opcode and some fixes * [RV64_DYNAREC] Added D1 /{5,7} opcode
* [RV64_DYNAREC] Optimize MOV64 emitter (#572)Yang Liu2023-03-163-41/+48
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* [RV64_DYNAREC] Added F3 0F 1E NOP opcode (#570)Yang Liu2023-03-163-3/+76
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* [RV64_PRINTER] Added C2/RETN and C3/RET opocde, along with fixes to jmp_to_nextptitSeb2023-03-153-15/+151
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* [RV64_DYNAREC] A few more fixes to the printerptitSeb2023-03-151-1/+3
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* [RV64_DYNAREC] Update rv64_printer with new reg allocationptitSeb2023-03-151-2/+2
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* [RV64_DYNAREC] Added CC (and NativeCall) opcode, and shuffle around some ↵ptitSeb2023-03-156-24/+84
| | | | xFlags /xRIP and x6 mapping
* [RV64_DYNAREC] Implemented a solutionfor the problematic F_OF flag (use ↵ptitSeb2023-03-156-6/+68
| | | | F_OF2 now)
* [RV64_DYNAREC] Added E8 CALL opcode, and fixed some issue with many macrosptitSeb2023-03-156-19/+329
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* [RV64_DYNAREC] Added 80 /7 CMP opcode (#567)Yang Liu2023-03-154-11/+120
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* [RV64_DYNAREC] Added C6 MOV opcode (#566)Yang Liu2023-03-151-0/+39
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* [RV64_DYNAREC] Added 39 CMP opcode and some fixes (#565)Yang Liu2023-03-154-55/+119
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* Added 66 0F 38 29 PCMPEQQ opcde ([ARM64_DYNAREC] too) (for #558)ptitSeb2023-03-142-0/+16
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* [RV64_DYNAREC] Added {81,83} /0 ADD opcode (#564)xctan2023-03-144-1/+110
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* [RV64_DYNAREC] Added 85 TEST opcode (#563)Yang Liu2023-03-143-2/+63
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* [RV64_DYNAREC] Added C1 /7 SAR opcode (#559)xctan2023-03-144-4/+107
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* [RV64_DYNAREC] Small optimization for 31 XOR opcode (#561)Yang Liu2023-03-141-6/+11
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* [RV64_DYNAREC] Added 31 XOR opcode (#560)Yang Liu2023-03-144-18/+88
| | | | | * [RV64_DYNAREC] Move things around * [RV64_DYNAREC] Added 31 XOR opcode
* [ARM64_DYNAREC] Small optim when putting 0 in a memory locationptitSeb2023-03-131-6/+14
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* [ARM64_DYNAREC] Use STUR/LDUR when possible, plus some other small improvmentsptitSeb2023-03-1322-463/+590
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* [ARM64_DYNAREC] Optimised double push/pop with stp/ldp opcodeptitSeb2023-03-133-11/+70
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* [ARM64_DYNAREC] Removed child leftover, it's not implemented anymoreptitSeb2023-03-134-26/+0
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* [RV64_DYNAREC] Removed child leftover, it's not implemented anymoreptitSeb2023-03-134-19/+0
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* [RV64_DYNAREC] Some small optim to getedptitSeb2023-03-131-11/+34
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* [RV64_DYNAREC] Fixed scratch register conflict for SUB (#556)Yang Liu2023-03-132-3/+3
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* [RV64_DYNAREC] Added 1 more scratch register (it was already saved/restored)ptitSeb2023-03-131-0/+1
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* [RV64_DYNAREC] Fixed rv64_epilog_fast, but it's not used for nowptitSeb2023-03-131-6/+13
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* [RV64_DYNAREC] Added 8B MOV opcode (#555)xctan2023-03-132-0/+15
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* [DYNAREC] Fixed missing X_PEND need at end of block for unimplemented opcodeptitSeb2023-03-131-1/+13
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* [ARM64_DYNAREC] Added unimplemented handling of CRC32 opcode (to avoid ↵ptitSeb2023-03-131-0/+36
| | | | stopping blocks)
* [RV64_DYNAREC] Added (81/83) SUB opcode (#554)Yang Liu2023-03-133-42/+108
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* [RV64_DYNAREC] Added 29 SUB opcode (#553)Yang Liu2023-03-135-15/+168
| | | | | * [RV64_DYNAREC] Added 29 SUB opcode * [RV64_DYNAREC] Clear flags if needed
* Tried to optimize TLS fetchingptitSeb2023-03-124-18/+20
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* Cleanup mutex wrappingptitSeb2023-03-124-70/+6
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* [DYNAREC] Fix some potential issue in the next jump handlingptitSeb2023-03-121-5/+7
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* [ARM64_DYNAREC] Added 66 0F 3A 0A opcodeptitSeb2023-03-121-1/+19
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* [ARM64_DYNAREC] Added (F2/F3) A7 opcodeptitSeb2023-03-121-1/+39
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* Expose POPCNT capability tooptitSeb2023-03-122-1/+2
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* [ARM64_DYNAREC] Added 66 0F 3A 0E opcodeptitSeb2023-03-121-0/+36
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* [ARM64_DYNAREC] Added F4 opcodeptitSeb2023-03-121-0/+11
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* Added support for SSE4.1, and added a couple of opcode ([ARM64_DYNAREC] too)ptitSeb2023-03-125-2/+47
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* [ARM64_DYNAREC] Fixed buildptitSeb2023-03-124-1/+32
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* [DYNAREC] Some renaming for the sake of consistancyptitSeb2023-03-127-26/+12
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* Rv64 dynarec (#550)ptitSeb2023-03-1233-54/+3624
| | | | | | | | | | | | | | * [RV64_DYNAREC] Pushed the rv64_lock.h * [RV64_DYNAREC] Add initial support for atomic functions * [RV64_DYNAREC] Added some basic infrastructure for the Dynarec (and 1 opcode) * [RV64_DYNAREC] Add a disassembler for RV64 instructions * [RV64_DYNAREC] Added 86 MOV opcode, and some fixes too * [RV64_DYNAREC] Added 8D LEA opcode * [RV64_DYNAREC] Added POP reg opcode * [RV64_DYNAREC] Various fixes and small optims --------- Co-authored-by: Yang Liu <liuyang22@iscas.ac.cn>
* [DYNAREC] Small optim for 66 0F 6D opcodeptitSeb2023-03-111-1/+3
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* [DYNAREC] Soma need FASTROUND disabled for it's physics engineptitSeb2023-03-111-0/+3
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* Start of new dev. cycleptitSeb2023-03-111-1/+1
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* Bumped to v0.2.2ptitSeb2023-03-101-1/+1
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* Added 2 more wrapped function to libgnutls (for #210)ptitSeb2023-03-091-2/+5
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* Added libresolv to libc for glibc2.34+ (might help #210)ptitSeb2023-03-091-1/+2
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